Prosecution Insights
Last updated: October 23, 2026
Application No. 18/702,558

SEMICONDUCTOR MODULE

Non-Final OA §102§103
Filed
Apr 18, 2024
Priority
Oct 26, 2021 — JP 2021-175054 +1 more
Examiner
ROLAND, CHRISTOPHER M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Ltd.
OA Round
1 (Non-Final)
65%
Grant Probability
Moderate
1-2
OA Rounds
8m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 65% of resolved cases
65%
Career Allowance Rate
362 granted / 560 resolved
-3.4% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
33 currently pending
Career history
599
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
51.4%
+11.4% vs TC avg
§102
21.0%
-19.0% vs TC avg
§112
24.6%
-15.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 560 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of species a, FIG. 4, claims 1-4, in the reply filed on 28 July 2026 is acknowledged. Claims 5 and 6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 28 July 2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement Information disclosure statement filed 18 April 2024 has been fully considered. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR MODULE COMPRISING A COOLER. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dung et al. (Japanese Kokai Publication 2003-249599, hereinafter Dung ‘599) of record. With respect to claim 1, Dung ‘599 teaches (FIGs. 2-5) a semiconductor module as claimed, comprising: a circuit body (207 and 208) having a semiconductor element (207), and a plurality of external terminals (209) to be connected to the semiconductor element ([0007, 0018-0019]); a substrate (1) having a power wiring layer (3) to be connected to the external terminals (209) ([0007, 0018-0019]); an insulating filling member (210) for covering a connection part between the external terminals (209) and the power wiring layer (3) ([0007, 0018-0019]); a cooler (6) having one surface side on which the circuit body (207 and 208) and the substrate (1) are mounted ([0007, 0018-0019]); and a heat dissipation member (10) disposed between the cooler (6) and the substrate (1) ([0007, 0018-0019]), wherein the heat dissipation member (10) forms a frame part on the cooler (6) so as to enclose an outer periphery of a region where the circuit body (207 and 208) is mounted ([0007, 0018-0019]), and the filling member (210) is filled into an inner peripheral side of the frame part ([0007, 0018-0019]). With respect to claim 2, Dung ‘599 teaches wherein the substrate (1) has a through hole (2) through which the filling member (210) is filled into the inner peripheral side of the frame part ([0007, 0018-0019]). With respect to claim 3, Dung ‘599 teaches wherein the circuit body (207 and 208) is disposed at an inner side of the through hole (2) formed in the substrate (1) ([0007, 0018-0019]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Dung ‘599 as applied to claim 3 above, and further in view of Bayerer (US Patent Application Publication 2014/0035118, hereinafter Bayerer ‘118). With respect to claim 4, Dung ‘599 teaches the device as described in claim 3 above with the exception of the additional limitation wherein a part of the substrate is disposed so as to cover the circuit body. However, Bayerer ‘118 teaches (FIG. 1) a substrate (7 or 10) having a connection element (4) to be connected to external terminals (21), wherein a part of the substrate is disposed so as to cover a circuit body (1) to provide electrical contact through a closed or partially-closed semiconductor package ([0043, 0047-0048]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a part of the substrate of Dung ‘599 disposed so as to cover the circuit body as taught by Bayerer ‘118 to provide electrical contact through a closed or partially-closed semiconductor package. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.R./Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Apr 18, 2024
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772813
BOTTOM DIELECTRIC ISOLATION INTEGRATION WITH BURIED POWER RAIL
4y 11m to grant Granted Oct 20, 2026
Patent 12765372
EMBEDDED AND PACKAGED HEAT DISSIPATION STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR
2y 9m to grant Granted Oct 13, 2026
Patent 12733500
SEAL STRUCTURES INCLUDING PASSIVATION STRUCTURES
4y 5m to grant Granted Sep 08, 2026
Patent 12733240
STRUCTURE WITH SELF-ALIGNED OFFSET GATE CONTACT AND DIRECT BACKSIDE CONTACT
3y 0m to grant Granted Sep 08, 2026
Patent 12707648
BIT-LINE RESISTANCE REDUCTION
4y 5m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
65%
Grant Probability
86%
With Interview (+20.9%)
3y 2m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 560 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month