DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The Information Disclosure Statement filed on 18 Apr 2024 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 11-14, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ke et al. (Pub. No. US 2019/0065332).
Claim 1:
Ke et al. disclose an apparatus, comprising:
a memory device comprising a plurality of superblocks [fig. 1; par. 0018 – “The flash memory 140 includes a plurality of planes 160˜16N. Specifically, each of the super blocks 160˜16N includes a plurality of blocks 16N_A˜16N_Z. In another embodiment, the flash memory 140 has four super blocks (CE0˜CE3). The storage plane 160 includes the blocks 160_A˜160_Z, and the storage plane 16N includes the blocks 16N_A˜16N_Z. Regarding the storage plane 160, each of the blocks 160_A˜160_Z further includes a plurality of pages. The block 160_A includes the pages 160_A_1˜160_A_X, and the block 160_Z includes the pages 160_Z_1˜160_Z_X. In addition, the pages 160_A_1˜16N_Z_X are physical pages. When the controller 120 performs a write operation or a programming operation on the flash memory 140, it controls the flash memory 140 to perform the write or programming operation with the unit of a physical page.”]; and
a controller coupled with the memory device and configured to cause the apparatus to [fig. 1; pars. 0016-0017 – controller 120]:
determine whether a first superblock comprises a first physical block of a first type and a second physical block of a first type, wherein the first superblock comprises a plurality of physical blocks that are each associated with a respective plane of the memory device [par. 0007 – It is determined whether a super block contains damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)];
determine whether a second superblock comprises a third physical block of a second type based at least in part on determining that the first superblock comprises the first physical block of the first type and the second physical block of the first type [par. 0007 – It is determined whether a second super block contains normal blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)];
replace the first physical block with the third physical block based at least in part on determining that the second superblock comprises the third physical block of the second type [par. 0007 – The normal blocks are used to replace the damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)]; and
access one or more physical blocks associated with the first superblock based at least in part on replacing the first physical block with the third physical block [pars. 0019-0037 – The replacement blocks are accessed according to the updated information in the tables. (“In one embodiment, a portion of the blocks in each storage plane 160˜16N constitutes a super block, and the flash memory 140 includes a plurality of super blocks. When a first block of at least one first super block of the super blocks is damaged, and a second block of a second super block on the position corresponding to the damaged block is normal, the controller 120 merges the second block of the second super block with the first super block to replace the first block. The RAM 180 stores a compression table DT to record position information about the first block in the first super block and the number information of the second block. In another embodiment, the RAM 180 stores a non-compression table NDT to record each position information of the first super block and the number information of its corresponding block. For example, the non-compression table NDT and the compression table DT are shown below:”)].
Claim 2 (as applied to claim 1 above):
Ke et al. disclose, wherein the controller is further configured to cause the apparatus to:
determine that a third superblock comprises a fourth physical block of the first type before determining that the first superblock comprises the first physical block and the second physical block of the first type [par. 0007 – It is determined whether a super block contains damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)];
determine that a fourth superblock comprises a fifth physical block of the second type based at least in part on determining that the third superblock comprises the fourth physical block of the first type [par. 0007 – It is determined whether another super block contains normal blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)]; and
replace the fourth physical block with the fifth physical block based at least in part on determining that the fourth superblock comprises the fifth physical block of the second type [par. 0007 – The normal blocks are used to replace the damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)].
Claim 3 (as applied to claim 2 above):
Ke et al. disclose, wherein:
the first superblock comprises an incomplete superblock based at least in part on replacing the first physical block with the third physical block [par. 0007 – Normal blocks are used to replace damaged blocks. A superblock may be considered incomplete when it still contains damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)]; and
the third superblock comprises a complete superblock based at least in part on replacing the fourth physical block with the fifth physical block [par. 0007 – Normal blocks are used to replace damaged blocks. A superblock may be considered complete when it no longer contains damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)].
Claim 4 (as applied to claim 1 above):
Ke et al. disclose, wherein the controller is further configured to cause the apparatus to:
determine that the first physical block and the third physical block are associated with a same plane of the memory device [par. 0007, 0021 – The blocks are replaced with blocks in the same position. Each position may be considered a plane. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)]; and
replace the first physical block with the third physical block based at least in part on determining that the first physical block and the third physical block are associated with the same plane of the memory device [par. 0007, 0021 – The blocks are replaced. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)].
Claim 5 (as applied to claim 4 above):
Ke et al. disclose, wherein the controller is further configured to cause the apparatus to:
determine that a plurality of superblocks associated with the memory device do not include a physical block of the second type associated with a same plane as the second physical block based at least in part on replacing the first physical block with the third physical block [par. 0007 – It is determined whether another super block contains normal blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)]; and
refrain from replacing the second physical block based at least in part on determining that the plurality of superblocks associated with the memory device do not include a physical block of the second type associated with a same plane as the second physical block [par. 0007 – The replacement block must be in the same position. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)].
Claim 7 (as applied to claim 1 above):
Ke et al. disclose, wherein replacing the first physical block with the third physical block is configured to cause the apparatus to:
update a mapping between the first physical block with a physical block address associated with the third physical block [pars. 0019-0037 – The tables are updated to reflect the block replacement. (“In one embodiment, a portion of the blocks in each storage plane 160˜16N constitutes a super block, and the flash memory 140 includes a plurality of super blocks. When a first block of at least one first super block of the super blocks is damaged, and a second block of a second super block on the position corresponding to the damaged block is normal, the controller 120 merges the second block of the second super block with the first super block to replace the first block. The RAM 180 stores a compression table DT to record position information about the first block in the first super block and the number information of the second block. In another embodiment, the RAM 180 stores a non-compression table NDT to record each position information of the first super block and the number information of its corresponding block. For example, the non-compression table NDT and the compression table DT are shown below:”)].
Claim 11 (as applied to claim 1 above):
Ke et al. disclose, wherein:
physical blocks of the first type comprise invalid physical blocks and physical blocks of the second type comprise valid physical blocks [par. 0007, 0019-0037 – Damaged blocks and normal blocks. The instant specification discloses that invalid may mean “bad, corrupt, or otherwise inaccessible”. [par. 0012]. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)].
Claim 12 (as applied to claim 1 above):
Ke et al. disclose,
wherein the first superblock comprises a plurality of physical blocks of the second type and the second superblock comprises a plurality of physical blocks of the first type [par. 0007, 0019-0037 – Each superblock may contain a number of damaged and normal blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)].
Claim 13 (as applied to claim 1 above):
Ke et al. disclose, wherein the controller is further configured to cause the apparatus to:
determine that a fifth superblock comprises a sixth physical block, a seventh physical block, and an eighth physical block of the first type based at least in part on replacing the first physical block with the third physical block [par. 0007 – It is determined whether a super block contains damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)];
determine that a sixth superblock comprises at least a ninth physical block of the second type based at least in part on determining that the fifth superblock comprises the sixth physical block, the seventh physical block, and the eighth physical block of the first type [par. 0007 – It is determined whether another super block contains normal blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)]; and
replace the eighth physical block with the ninth physical block based at least in part on determining that the sixth superblock comprises the ninth physical block of the second type [par. 0007 – The normal blocks are used to replace the damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)].
Claim 14 (as applied to claim 13 above):
Ke et al. disclose, wherein the controller is further configured to cause the apparatus to:
determine that a seventh superblock comprises at least a tenth physical block of the second type based at least in part on replacing the eighth physical block with the ninth physical block [par. 0007 – It is determined whether another super block contains normal blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)]; and
replace the seventh physical block with the tenth physical block based at least in part on determining that the seventh superblock comprises the tenth physical block of the second type [par. 0007 – Normal blocks are used to replace damaged blocks. A superblock may be considered complete when it no longer contains damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)], wherein the fifth superblock comprises an incomplete superblock based at least in part on replacing the seventh physical block with the tenth physical block [par. 0007 – Normal blocks are used to replace damaged blocks. A superblock may be considered incomplete when it still contains damaged blocks. (“Each of the storage planes comprises a plurality of blocks. The data storage method includes utilizing a portion of the blocks in each storage plane to constitute a super block, so that the flash memory comprises a plurality of super blocks; and when at least one first block of at least one first super block of the super blocks is damaged, and at least one second block of at least one second super block of the super blocks corresponding to the position of the damaged block is normal, the second block of the second super block is merged with the first super block to replace the first block; and position information of the first block in the first super block and number information of the second block are recorded in a compression table.”)].
Claim 17:
Claim 17, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis [par. 0044].
Claim 18 (as applied to claim 17 above):
Claim 18, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 2 above, mutatis mutandis.
Claim 19 (as applied to claim 18 above):
Claim 19, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 3 above, mutatis mutandis.
Claim 20:
Claim 20, directed to a method, is rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ke et al. (Pub. No. US 2019/0065332) as applied to claim 1 above, and further in view of Radke et al. (Pub. No. US 2009/0300269).
Claim 8 (as applied to claim 1 above):
Ke et al. disclose, wherein the controller is further configured to cause the apparatus to:
receive an access command associated with the first physical block based at least in part on replacing the first physical block with the third physical block, the access command comprising a first virtual address;
However, Ke et al. do not specifically disclose,
determine whether the first virtual address satisfies a threshold value based at least in part on receiving the access command.
In the same field of endeavor, Radke et al. disclose,
determine whether the first virtual address satisfies a threshold value based at least in part on receiving the access command [pars. 0025-0026 – “The controller also tracks and maintains (e.g., updates) 208/216 the usage table data for LBAs of the memory device during operation. If the usage of an LBA currently assigned to MLC memory exceeds some threshold value 210, the controller will attempt to move the data associated with the LBA (and reassign the LBA to the location in) to SLC memory 212. In one embodiment, this threshold value may be 1000 write operations performed on a given LBA.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ke et al. to include migrating data, as taught by Radke et al., in order to improve performance but storing frequently accessed data in higher speed memory.
Claim 9 (as applied to claim 8 above):
Radke et al. disclose, wherein the controller is further configured to cause the apparatus to:
access a first physical block address of the memory device based at least in part on determining that the first virtual address satisfies the threshold value [pars. 0025-0026 – “The controller also tracks and maintains (e.g., updates) 208/216 the usage table data for LBAs of the memory device during operation. If the usage of an LBA currently assigned to MLC memory exceeds some threshold value 210, the controller will attempt to move the data associated with the LBA (and reassign the LBA to the location in) to SLC memory 212. In one embodiment, this threshold value may be 1000 write operations performed on a given LBA. The embodiments however are not limited to a single threshold value. For example, the threshold value may be some fraction of the total write operations performed on the memory 212. If the usage for all the LBAs assigned to MLC memory remain less than the threshold value, then those LBAs will continue to be assigned to the MLC memory.”].
Claim 10 (as applied to claim 8 above):
Radke et al. disclose, wherein the controller is further configured to cause the apparatus to:
access a second physical block address of the memory device based at least in part on determining that the first virtual address does not satisfy the threshold value [pars. 0025-0026 – “The controller also tracks and maintains (e.g., updates) 208/216 the usage table data for LBAs of the memory device during operation. If the usage of an LBA currently assigned to MLC memory exceeds some threshold value 210, the controller will attempt to move the data associated with the LBA (and reassign the LBA to the location in) to SLC memory 212. In one embodiment, this threshold value may be 1000 write operations performed on a given LBA. The embodiments however are not limited to a single threshold value. For example, the threshold value may be some fraction of the total write operations performed on the memory 212. If the usage for all the LBAs assigned to MLC memory remain less than the threshold value, then those LBAs will continue to be assigned to the MLC memory.”.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ke et al. (Pub. No. US 2019/0065332) as applied to claim 1 above, and further in view of Li et al. (Pub. No. US 2017/0294237).
Claim 15 (as applied to claim 1 above):
Ke et al. disclose all the limitations above but do not specifically disclose, wherein the controller is further configured to cause the apparatus to:
scan a plurality of superblocks associated with the memory device to identify physical blocks of the first type and of the second type, wherein determining that the first superblock comprises the first physical block and the second physical block of the first type is based at least in part on scanning the plurality of superblocks.
In the same field of endeavor, Li et al. disclose,
scan a plurality of superblocks associated with the memory device to identify physical blocks of the first type and of the second type, wherein determining that the first superblock comprises the first physical block and the second physical block of the first type is based at least in part on scanning the plurality of superblocks [pars. 0006, 0026, 0032-0040 – “Background media scan (BGMS) can be performed to periodically monitor the reliability of the data written to the flash memory during idle/free time. It can detect performance degradation on NAND superblocks due to retention, and refresh (garbage collect) the superblock. If the refresh cannot improve the performance, the block can be retired when necessary.” … “Typically, the flash memory devices can be scanned periodically to detect bad blocks and retire them as needed. For example, a process known as background media scan (BGMS) can be executed to perform error detection and correction in the background. In some embodiments, the flash memory controller 106 may perform an improved BGMS process that can predict which word-line for a flash memory block is to be developed into a bad word-line. The bad word-line may correspond to an MSB page or an LSB page. Accordingly, the BGMS process can retire the flash memory block that includes the bad word-line, after recovering the data. This is further explained with reference to a flow chart in FIG. 3.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ke et al. to include scanning blocks, as taught by Li et al., in order to improve data integrity by proactively retiring defective blocks.
Claim 16 (as applied to claim 15 above):
Ke et al. disclose, wherein the controller is further configured to cause the apparatus to:
assign each superblock of the plurality of superblocks to one or more slots associated with the memory device based at least in part on scanning the plurality of superblocks, wherein each slot of the one or more slots is associated with superblocks having a respective quantity of physical blocks of the first type [pars. 0006, 0026, 0032-0040 – Superblocks are either active or retired. (“Background media scan (BGMS) can be performed to periodically monitor the reliability of the data written to the flash memory during idle/free time. It can detect performance degradation on NAND superblocks due to retention, and refresh (garbage collect) the superblock. If the refresh cannot improve the performance, the block can be retired when necessary.” … “Typically, the flash memory devices can be scanned periodically to detect bad blocks and retire them as needed. For example, a process known as background media scan (BGMS) can be executed to perform error detection and correction in the background. In some embodiments, the flash memory controller 106 may perform an improved BGMS process that can predict which word-line for a flash memory block is to be developed into a bad word-line. The bad word-line may correspond to an MSB page or an LSB page. Accordingly, the BGMS process can retire the flash memory block that includes the bad word-line, after recovering the data. This is further explained with reference to a flow chart in FIG. 3.”)].
Allowable Subject Matter
Claim 6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not disclose the limitations of the listed claims in conjunction with the limitations of the base claim and intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Muchherla et al. (Pub. No. US 2023/0195341) disclose, “Aspects of the present disclosure address the above and other deficiencies with a memory sub-system that can reconfigure incomplete super blocks into complete super blocks and can perform operations on incomplete super blocks. More specifically, embodiments of the present disclosure can reassign orphan blocks within a plane from one incomplete super block to fill/complete another incomplete super block to complete the second super block allow for full parallelism on the completed super block (i.e., allow for a maximum number of parallel operations to be performed on the complete super block). Moreover, in embodiments of the present disclosure, data is written in SLC mode to complete super blocks and then to incomplete super blocks prior to being written in TLC mode, or another mode (e.g., MLC/QLC) to complete super blocks. For the purposes of this disclosure, wherever TLC mode is referenced, it can be replaced with MLC mode, QLC mode, or modes using higher number of logical levels per cell. In this manner a larger amount of data is written to the memory device at a faster rate than in various other system”. [par. 0021]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
28 February 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139