DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed September 29, 2026 has been entered. Claims 1 and 4-14 remain pending in this application. Claims 6-14 drawn to non-elected invention have been withdrawn. Claims 1 and 4-5 have been amended. Claims 2-3 cancelled at applicant’s request. No claims have been added. No new matter has been added.
Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed September 2, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0276120 A1 to Ed Hsia, et al. (hereafter Hsia) in view of US 2013/0107628 A1 to Yingda Dong, et al. (hereafter Dong) and further in view of US 7,522,457 B2 to Gerrit Jan Hemink, et al. (hereafter Hemink).
Regarding Amended Independent Claim 1, Hsia discloses a multi-level implementing method in a 3D flash memory (Disclosing a multi-level method for programming 3D flash memory: Hsia, ¶[0013]), the method comprising:
securing a threshold voltage distribution region (Distributing voltage thresholds within a bounded region: Hsia, ¶[0034])
by narrowing a distribution (Forming compact voltage threshold distributions: Hsia, ¶[0032]) of an erase threshold voltage (Specifically forming narrow erase distributions: Hsia, ¶[0030])
during an erase operation of the 3D flash memory (Disclosing the process of narrow erase voltage thresholds in the context of an erase operation: Hsia, Figure 4A); and
setting multi-level program threshold voltages in the secured threshold voltage distribution region (Setting the remaining voltage thresholds evenly in the available voltage distribution region: Hsia, ¶[0034]),
wherein the securing includes:
applying an initial erase voltage to a selected word line (Disclosing an initial erase pulse: Hsia, ¶[0043])
corresponding to a memory cell that is a target of the erase operation among a plurality of word lines included in the 3D flash memory (Applying the initial erase pulse to an array or portions of an array as the target of the erase operation: Hsia, ¶[0044]);
applying a read voltage to the selected word line (Disclosing ‘testing’ – reading – the erased memory cells: Hsia¶[0044]); and
applying an additional erase voltage to the selected word line (Applying additional erase pulses to the targeted memory cells: Hsia, ¶[0044]),
wherein the initial erase voltage, the read voltage, and the additional erase voltage are applied to the same selected word line corresponding to the memory cell that is the target of the erase operation (Hsia, ¶[0044]),
wherein the applying of the read voltage and the applying of the additional erase voltage are sequentially repeated until the distribution of the erase threshold voltage is narrowed to a level of a distribution of one of the multi-level program threshold voltages (Erasing memory cells to a tight, low sigma, distribution of erasure approximately equivalent to narrow program Vt distributions: Hsia, ¶[0030]).
Hsia fails to teach a 3D flash memory architecture wherein the 3D flash memory includes a substrate, a plurality of word lines extending in a horizontal direction, a plurality of interlayer insulating layers alternately stacked with the plurality of word lines in a vertical direction, and a plurality of vertical channel structures extending in the vertical direction through the plurality of word lines and the plurality of interlayer insulating layers, wherein the vertical direction is perpendicular to a top surface of the substrate, and the horizontal direction is parallel to the top surface of the substrate. Dong, however, discloses a 3D flash memory wherein:
wherein the 3D flash memory includes
a substrate (A substrate: Dong, ¶[0043]),
a plurality of word lines extending in a horizontal direction (Word lines extending horizontal to the substrate: Dong, ¶[0043]),
a plurality of interlayer insulating layers alternately stacked with the plurality of word lines in a vertical direction (Alternating insulating layers and conductive word lines: Dong, ¶[0043]; Dong does not expressly describe the alternating layers as insulating, but the insulating properties of the alternate layers are necessary for proper signal propagation), and
a plurality of vertical channel structures extending in the vertical direction through the plurality of word lines and the plurality of interlayer insulating layers (A plurality of vertical channel structures through the alternating layers: Dong, ¶[0043]),
wherein the vertical direction is perpendicular to a top surface of the substrate, and the horizontal direction is parallel to the top surface of the substrate (Disclosing the wordlines being horizontal, i.e. on plane with, the substrate. Vertical is definitionally normal to horizontal: Dong, ¶[0043]),
Dong teaches this 3D architecture avoids the inconvenience and lack of flexibility typically present in 3D NAND flash memory and allows erase operation be performed in groups of memory cells smaller than a block (Dong, ¶[0041]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of this application, to combine the reduced erase block size architecture of Dong with the narrowed erase voltage threshold methodology of Hsia, with a reasonable expectation of success. Both inventions were well known in the field of NAND Flash erase operation optimization and the combination of known inventions with predictable results is obvious and not patentable.
Neither Hsia nor Dong teach sequentially applying the erase and read operations, wherein the additional erase voltage has a value smaller than the initial erase voltage. Hemink, however, discloses an erase operation wherein:
wherein the applying of the read voltage and the applying of the additional erase voltage are sequentially repeated (Iteratively applying erase pulse and verification operations: Hemink, col.14:47-65)
wherein, in each repetition of the applying of the read voltage and the applying of the additional erase voltage, the distribution of the erase threshold voltage is narrower than a distribution of the erase threshold voltage resulting from an immediately preceding erase-voltage application (Reducing the voltage of each erase pulse allowing more accurate control of the erase operation, resulting in erase threshold voltage distributions more accurately positioned near the Everify level: Hemink, col.15:1-7), and
wherein the additional erase voltage has a value smaller than the initial erase voltage (Decreasing the subsequent erase pulse: Hemink, col.14:56-57).
Hemink teaches reducing the size of the erase pulses allows for better control of the shift in threshold voltage, allowing more accurate control of the shift (Hemink, col.15:1-7). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the accurate erase method of Hemink with the narrowed erase voltage threshold methodology of Hsia, with a reasonable expectation of success. Both inventions were well known in the field of NAND flash erase operation optimization and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 4, Hemink discloses an erase operation as in Claim 1, wherein
the additional erase voltage applied in a subsequent repetition has a smaller value than the additional erase voltage applied in an immediately preceding repetition (Iteratively reducing the voltage of each erase pulse: Hemink, col.14:66-15:7).
Regarding Amended Claim 5, Hemink discloses an erase operation as in Claim 1, wherein
each application of the additional erase voltage narrows the distribution of the erase threshold voltage to one-half of a distribution level of the erase threshold voltage resulting from an immediately preceding erase voltage application (Reducing the voltage of each erase pulse allowing more accurate control of the erase operation, resulting in erase threshold voltage distributions more accurately positioned near the Everify level: Hemink, col.15:1-7).
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7,057,936 B2 to Toshitake Yaegashi, et al.: Teaching reducing the relative voltage of iterative erase pulses to narrow the voltage distribution of memory cells.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 10/14/2026
