DETAILED ACTION
1. This Office Action is responsive to claims filed for App. 18/702,984 on April 14, 2026. Claims 1, 3-9 and 11-16 are pending. Please note Claims 13-16 have been withdrawn in light of an earlier restriction requirement.
America Invents Act
2. The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 3, 9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. ( US 2021/0027720 A1 ).
Park teaches in Claim 1:
A display device, comprising a display panel and a driving module; wherein the display panel comprises a first display area, a second display area, and a plurality of rows and columns of pixel circuits ( Figures 3, 4 and 17, [0053]+ disclose a display panel 110c which can drive two image portions, as shown. For purposes of examination, please note first partial panel region PPR1c as the first display area and second partial panel region PPR2c as the second display area. This is not meant to be limiting as Figure 17 shows further partial regions, for example. Figure 4 shows a pixel PX and Figure 1 shows a plurality of these pixels, arranged in a matrix of rows and columns ); and
the driving module is configured to control a refresh frequency of the pixel circuits provided in the first display area to be a first refresh frequency, and control a refresh frequency of the pixel circuits provided in the second display area to be different from the first refresh frequency ( Figure 7, [0066] disclose PPR1 is driven at a first frequency, such as 120Hz and PPR2 is driven at a second frequency 15Hz )
wherein the driving module is configured to, when it is determined that a picture displayed in a part of the display area comprised in the display panel changes and a picture displayed in the other part of the display area comprised in the display panel does not change ( Figure 5, [0062] disclose a still image detecting block 154 which can calculate aspects of the frame data, such as moving data versus still image data and in the partial regions of the display, as shown in Figure 3 ), control a refresh frequency of the pixel circuits in the part of the display area to be a first refresh frequency, and control a refresh frequency of the other part of the display area to be less than the first refresh frequency; the part of the display area is an updated display area, and the other part of the display area is a non-updated display area; the updated display area is the first display area, and the non-updated display area is the second display area. ( As disclosed above, Figure 7 shows the two regions, corresponding to a moving image and still image, are set at 120Hz and 15Hz, respectively. Please note the still image area is a non-updated display area as the contents have been determined to not be changing, etc. Please note the frequency of the still image area is less than the frequency of the moving image area )
Park teaches in Claim 3:
The display device according to claim 1, wherein the driving module is further configured to, when at least one row of pixel circuits is provided in the updated display area, adjust a refresh frequency of the at least one row of pixel circuits in the updated display area by controlling a frequency of a first start signal and a frequency of a second start signal. ( Figures 17 and 18 show multiple partial regions, such as PPR1-PPR4. For the moving image aspects, such as PPR1 and PPR3, higher frequencies are driven and it is clear that there are multiple start signals for these partial regions )
Park teaches in Claim 9:
A refresh driving method applied to a display device, wherein the display device comprises a display panel and a driving module; the display panel comprises a first display area, a second display area, and a plurality of rows and columns of pixel circuits ( Figures 3, 4 and 17, [0053]+ disclose a display panel 110c which can drive two image portions, as shown. For purposes of examination, please note first partial panel region PPR1c as the first display area and second partial panel region PPR2c as the second display area. This is not meant to be limiting as Figure 17 shows further partial regions, for example. Figure 4 shows a pixel PX and Figure 1 shows a plurality of these pixels, arranged in a matrix of rows and columns ); the refresh driving method comprising:
controlling, by the driving module, a refresh frequency of the pixel circuits provided in the first display area to be a first refresh frequency, and controlling, by the driving module, a refresh frequency of the pixel circuits provided in the second display area to be different from the first refresh frequency ( Figure 7, [0066] disclose PPR1 is driven at a first frequency, such as 120Hz and PPR2 is driven at a second frequency 15Hz )
wherein the refresh driving method further comprises:
when it is determined that a picture displayed in a part of the display area comprised in the display panel changes and a picture displayed in the other part of the display area comprised in the display panel does not change ( Figure 5, [0062] disclose a still image detecting block 154 which can calculate aspects of the frame data, such as moving data versus still image data and in the partial regions of the display, as shown in Figure 3 ), controlling a refresh frequency of the pixel circuits in the part of the display area to be a first refresh frequency, and controlling a refresh frequency of the other part of the display area to be less than the first refresh frequency; wherein the part of the display area is an updated display area, and the other part of the display area is a non-updated display area; the updated display area is the first display area, and the non-updated display area is the second display area. ( As disclosed above, Figure 7 shows the two regions, corresponding to a moving image and still image, are set at 120Hz and 15Hz, respectively. Please note the still image area is a non-updated display area as the contents have been determined to not be changing, etc. Please note the frequency of the still image area is less than the frequency of the moving image area )
Park teaches in Claim 11:
The refresh driving method according to claim 9, comprising: when at least one row of pixel circuits is provided in the updated display area, adjusting a refresh frequency of the at least one row of pixel circuits in the updated display area by controlling a frequency of a first start signal and a frequency of a second start signal. ( Figures 17 and 18 show multiple partial regions, such as PPR1-PPR4. For the moving image aspects, such as PPR1 and PPR3, higher frequencies are driven and it is clear that there are multiple start signals for these partial regions )
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 4-8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al.
( US 2021/0027720 A1 ) in view of Wang et al. ( CN 11286448 A ). Please note a copy of Wang has been provided in the file wrapper.
As per Claim 4:
Park does not explicitly teach “wherein the driving module comprises a first update GOA module and a second update GOA module; the first update GOA module is configured to provide an N-type scanning signal for the at least one row of pixel circuits; the second update GOA module is configured to provide a P-type scanning signal for the at least one row of pixel circuits; the first update GOA module comprises multiple stages of first update GOA circuits, and the second update GOA module comprises a plurality of groups of second update GOA circuits; a first-stage first update GOA circuit included in the first update GOA module is connected to the first start signal, and a first-stage second update GOA circuit included in the second update GOA module is connected to the second start signal.”
However, in the same field of endeavor, gate driving circuits, Wang teaches of a plurality of GOA circuits, ( Wang, Figures 4-8 ). Notably, the combination teaches:
“wherein the driving module comprises a first update GOA module and a second update GOA module ( Wang, Figure 5 discloses a first gate driving circuit comprises 21N (read as a first update GOA module) and 22P (read as a second update GOA module) ); the first update GOA module is configured to provide an N-type scanning signal for the at least one row of pixel circuits; the second update GOA module is configured to provide a P-type scanning signal for the at least one row of pixel circuits ( Figure 5, [0069] disclose 21N provides a signal Scan1 to N-type transistor T4 and 22P provides a signal Scan2 to P-type transistor T2 ); the first update GOA module comprises multiple stages of first update GOA circuits, and the second update GOA module comprises a plurality of groups of second update GOA circuits ( [0074] discloses a plurality of cascaded gate driving circuit units for both of 21N and 22P ); a first-stage first update GOA circuit included in the first update GOA module is connected to the first start signal, and a first-stage second update GOA circuit included in the second update GOA module is connected to the second start signal ( Respectfully, it is clear these various drivers have an initialization signal, etc. Furthermore, Park teaches in Figure 5 of various signals which are sent to the drivers, such as SS1F1/2, PDAT1/2, etc )”
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the GOA drivers, as taught by Wang, with the motivation that multiple GOA drivers can be used to drive particular N and P type pixels, ( Wang, [0069]+ ). Thus, different types of pixels, and the advantages of N and P type circuits can be effectively used.
Park teaches in Claim 5:
The display device according to claim 3, wherein two adjacent pixel circuit groups adjacent to the at least one row of pixel circuits in the updated display area are provided in the non-updated display area; the adjacent pixel circuit group comprises at least one row of transition pixel circuits ( Figure 18, [0096] disclose multiple boundary portions BP1, BP2, BP3, etc, (read as transition pixel circuits. Furthermore, Figure 3 shows one such section as well. Furthermore, please note multiple still image areas, as shown in Figure 18, i.e. two adjacent pixel circuit groups in the non-updated display area. Furthermore, another interpretation is shown in Figure 12 with a plurality of adjacent signal lines within DF1 and DF2 ); and
the driving module is configured to control a refresh frequency of the at least one row of transition pixel circuits to be a second refresh frequency, wherein the second refresh frequency is less than the first refresh frequency, and the second refresh frequency is greater than the refresh frequency of the other part of the display area. ( Figures 7 and 18 shows the frequency of the boundary area to be between DF1 and DF3, i.e. the frequencies of the other partial regions, including “the other part of the display area” )
Park teaches in Claim 6:
The display device according to claim 5, wherein non-adjacent pixel circuit groups other than the adjacent pixel circuit groups are further provided in the non-updated display area; the non-adjacent pixel circuit group comprises at least one row of pixel circuits; and the driving module is configured to control a refresh frequency of pixel circuits included in the non-adjacent pixel circuit group to be a third refresh frequency; and the third refresh frequency is less than the second refresh frequency. ( Respectfully, the same reasoning in Claim 5 are also applicable here as well: Figure 18, [0096] disclose multiple boundary portions BP1, BP2, BP3, etc, (read as transition pixel circuits. Furthermore, Figure 3 shows one such section as well. Furthermore, please note multiple still image areas, as shown in Figure 18, i.e. two adjacent pixel circuit groups in the non-updated display area. Furthermore, another interpretation is shown in Figure 12 with a plurality of adjacent signal lines within DF1 and DF2 )
Park teaches in Claim 7:
The display device according to claim 2, wherein when M rows and N columns of pixel circuits are provided in the updated display area, and N is less than a total number of columns of pixel circuits comprised in the display panel, the pixel circuit comprises a writing control circuit ( Figure 1 shows a controller 140, i.e. a writing control circuit, which provides signals to the drivers 120 and 130 ); M and N are positive integers;
a control end of the writing control circuit is electrically connected to a writing control line, a first end of the writing control circuit is electrically connected to a data line, and a second end of the writing control circuit is electrically connected to a data writing node; the writing control circuit is configured to control connection between the data line and the data writing node under control of a writing control signal provided by the writing control line ( Figure 1 shows the output of controller 140 to data driver 120 and scan driver 130, which make up data and scan lines. These show at the pixel circuit in Figure 4 );
the driving module is configured to control a frequency of the writing control signal connected to the control end of the writing control circuit included in pixel circuits located in a same row but in different columns in the M rows and N columns of pixel circuits, to enable a refresh frequency of the pixel circuits located in the same row but in different columns in the M rows and N columns of pixel circuits to be less than the first refresh frequency. ( Figure 7 shows the various signal lines for the different regions, as does Figure 17. These lines correspond to different rows )
Park teaches in Claim 8:
The display device according to claim 7, wherein the driving module is further configured to control the frequency of a writing control signal connected to the control end of the writing control circuit comprised in the M rows and N columns of pixel circuits to enable the refresh frequency of the M rows and N columns of pixel circuits to be the first refresh frequency. ( Figure 12, [0081] disclose the various lines which are assigned different frequencies which are applied to the various rows. The data corresponds to the still image or moving image data and are applied to the columns through the data driver, again, realized at the pixel level. It is clear the type of data correspond to the assigned frequency )
As per Claim 12:
Park does not explicitly teach “wherein the display panel further comprises a first update GOA module and a second update GOA module, the first update GOA module is configured to provide an N-type scanning signal for the at least one row of pixel circuits, and the second update GOA module is configured to provide a P-type scanning signal for the at least one row of pixel circuits; the first update GOA module comprises multiple stages of first update GOA circuits, and the second update GOA module comprises a plurality of groups of second update GOA circuits; a first-stage first update GOA circuit included in the first update GOA module is connected to the first start signal, and a first-stage second update GOA circuit included in the second update GOA module is connected to the second start signal.”
However, in the same field of endeavor, gate driving circuits, Wang teaches of a plurality of GOA circuits, ( Wang, Figures 4-8 ). Notably, the combination teaches:
“wherein the display panel further comprises a first update GOA module and a second update GOA module ( Wang, Figure 5 discloses a first gate driving circuit comprises 21N (read as a first update GOA module) and 22P (read as a second update GOA module) ), the first update GOA module is configured to provide an N-type scanning signal for the at least one row of pixel circuits, and the second update GOA module is configured to provide a P-type scanning signal for the at least one row of pixel circuits ( Figure 5, [0069] disclose 21N provides a signal Scan1 to N-type transistor T4 and 22P provides a signal Scan2 to P-type transistor T2 ); the first update GOA module comprises multiple stages of first update GOA circuits, and the second update GOA module comprises a plurality of groups of second update GOA circuits ( [0074] discloses a plurality of cascaded gate driving circuit units for both of 21N and 22P ); a first-stage first update GOA circuit included in the first update GOA module is connected to the first start signal, and a first-stage second update GOA circuit included in the second update GOA module is connected to the second start signal. ( Respectfully, it is clear these various drivers have an initialization signal, etc. Furthermore, Park teaches in Figure 5 of various signals which are sent to the drivers, such as SS1F1/2, PDAT1/2, etc )”
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the GOA drivers, as taught by Wang, with the motivation that multiple GOA drivers can be used to drive particular N and P type pixels, ( Wang, [0069]+ ). Thus, different types of pixels, and the advantages of N and P type circuits can be effectively used.
Response to Arguments
8. Applicant’s arguments considered, but are respectfully not persuasive.
Please note the updated rejection in light of the claim amendments, notably incorporating the reasoning of Claim 2 into Claim 1 and Claim 10 into 9, respectively.
Park teaches, such as in Figure 3, of a still image, which is a non-updated region, versus a moving image, which is an updated region.
Applicant argues these regions are preset/fixed. However, Figure 5 teaches of a still image detector which can analyze the image data to determine/classify that particular partial region. If it not determined to be a still image, then the frequency will not be lowered. Park simply teaches of being able to determine a still image, and IF applicable, adjusts the frequency. The detector naturally means that it is not necessarily preset/fixed, but an analysis is performed to determine this aspect. Park teaches in [0012], etc, of dynamically changing the panel regions as well as the boundary. Again, Park simply teaches of determining image aspects and setting the frequency for those determined image aspects.
Conclusion
9. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621
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