DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 18/703,027 has a total of 15 claims pending in the application; there are 3 independent claims and 12 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statement 05/02/2024 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Breakstone et al. (US pub. 2017/0220505), hereinafter, “Breakstone”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claim 1, Breakstone discloses an electronic device (storage drive 110 of fig. 1, as discloses in paragraph 0026), comprising: a connector (main connector 115 of fig. 3 combined with M.2 connector 131; see paragraphs 0026 and 0033); a first switch to control, responsive to a signal, providing of a first voltage signal to the connector (see paragraph 0076); a second switch to control, responsive to the signal, providing of a second voltage signal to the connector (see paragraph 0076); and a controller to: determine, responsive to the signal, a type of a storage device coupled to the connector; and enable, responsive to the type of the storage device, a set of signals to the connector (see paragraph 0040-0042, which teach different storage drives of different voltage levels transmitting data to the main connector 115, M.2 connector 131).
3. As per claim 2, Breakstone discloses “The electronic device of claim 1” [See rejection to claim 1 above], wherein the signal is a voltage signal having a first voltage in response to the storage device having a first type and having a second voltage in response to the storage device having a second type (see paragraph 0062, which discloses “in some examples, bidirectional power flow is possible over link 623. Power can be accepted by storage device 610 when input power is available, such as from a mating connector. Power can be redistributed to other storage devices by module 610 over link 623 when input power is not available, such as during power interruption events. When storage device 610 is removed from a mating connector, then power can be bled off into associated power sink circuitry. Although one power link 623 is shown, it should be understood that more than one link can be included, such as separate input and output links or separate links for different voltage levels”).
4. As per claim 3, Breakstone discloses wherein the controller is to: enable, responsive to the type of the storage device indicating a first type of storage device, a first set of signals to the connector; and enable, responsive to the type of the storage device indicating a second type of storage device, a second set of signals to the connector (see paragraph 0040-0042).
5. As per claim 4, Breakstone discloses wherein the first set of signals traverse a first communications bus and the second set of signals traverse a second communications bus(see paragraph 0098).
6. As per claim 5, Breakstone discloses, comprising: a first buffer to control, responsive to the signal, transmission of the set of signals from the controller to the storage device; and a second buffer to control, responsive to the signal, the transmission of the set of signals from the storage device to the controller (see paragraph 0094).
7. As per claim 6, Breakstone discloses an electronic device (storage drive 110 of fig. 1, as discloses in paragraph 0026), comprising: a connector (main connector 115 of fig. 3 combined with M.2 connector 131; see paragraphs 0026 and 0033) having multiple terminals, the connector to couple to a storage device (see paragraphs 0026 and 0033); a transistor having a gate to receive a signal from a first terminal of the connector, a source coupled to a voltage supply circuit, and a drain coupled to a second terminal of the connector, the transistor to enable a voltage signal of the voltage supply circuit to propagate to the second terminal of the connector responsive to the signal having a value below a specified threshold (see paragraphs 0077, 0096 and 0111); and a buffer having a control input to receive the signal from the first terminal of the connector, a data input coupled to a controller, and an output coupled to a third terminal of the connector, the buffer to enable a set of signals to propagate from the controller to the third terminal of the connector responsive to the signal having the value below the specified threshold (see paragraph 0040-0042 and 0094).
8. As per claim 7, Breakstone discloses wherein responsive to the signal having a second value that is equivalent to or exceeds the specified threshold, the transistor is to disable the voltage signal of the voltage supply circuit from propagating to the second terminal of the connector and the buffer is to disable the set of signals from propagating from the controller to the third terminal of the connector (see paragraph 0108-0111).
9. As per claim 8, Breakstone discloses 8 comprising: a second transistor having a second gate to receive the signal from the first terminal of the connector, a second source coupled to the voltage supply circuit, and a second drain coupled to a fourth terminal of the connector; wherein the second transistor is to enable a second voltage signal of the voltage supply circuit to propagate to the fourth terminal of the connector responsive to the signal having the value below the specified threshold; and wherein the second transistor is to disable the second voltage signal of the voltage supply circuit from propagating to the fourth terminal of the connector responsive to the signal having a second value that is equivalent to or exceeds the specified threshold (see paragraph 0108-0111).
10. As per claim 9, Breakstone discloses wherein the controller is coupled to the voltage supply circuit, the controller to cause, responsive to the signal having the value below the specified threshold, the voltage supply circuit to supply the voltage signal and the second voltage signal to the source and the second source, respectively, of the transistor and the second transistor, respectively (see paragraph 0108-0111).
11. As per claim 10, Breakstone discloses, comprising: a second buffer having a second control input to receive the signal from the first terminal of the connector, a second data input coupled to the controller, and a second output coupled to a fourth terminal of the connector; wherein responsive to the signal having a second value that is equivalent to or exceeds the specified threshold, the second buffer is to enable a second set of signals to propagate from the fourth terminal of the connector to the controller; and wherein responsive to the signal having the value that is below the specified threshold, the second buffer is to disable the second set of signals from propagating from the fourth terminal of the connector to the controller (see paragraph 0108-0111).
12. As per claim 11, Breakstone discloses an electronic device (storage drive 110 of fig. 1, as discloses in paragraph 0026), comprising: a connector (main connector 115 of fig. 3 combined with M.2 connector 131; see paragraphs 0026 and 0033) to couple to a storage device, the coupling to provide a signal, the signal having a first value responsive to the storage device having a first type and a second value responsive to the storage device having a second type (see paragraphs 0026 and 0062); a first transistor to control, responsive to reception of the signal at a first gate, providing of a first voltage signal to the connector; a second transistor to control, responsive to reception of the signal at a second gate, providing of a second voltage signal to the connector (see paragraphs 0077, 0096 and 0111); and a buffer to control, responsive to reception of the signal at a control input, propagation of a set of signals between a controller and the connector (see paragraph 0040-0042 and 0094).
13. As per claim 12, Breakstone wherein the connector is an M.2 connector (see paragraph 0033).
14. As per claim 14, Breakstone discloses wherein the controller is to: enable, responsive to the signal having the first value, a first set of signals to traverse a first communications bus; enable, responsive to the signal having the second value, a second set of signals to traverse a second communications bus; and wherein the first communications bus and the second communications bus have an overlapping signal path (see paragraph 0094 and 0098).
Claim Rejections - 35 USC § 103
15. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
16. Claims 13 and 15 are rejected under 35 U.S.C. 103(a) as being unpatentable over Breakstone et al. (US pub. 2017/0220505), hereinafter, “Breakstone”, in view of Bhuiyan et al. (US pub. # 2015/0160706), hereinafter, “Bhuiyan”.
17. As per claim 13, Breakstone discloses “The electronic device of claim 11” [See rejection to claim 11 above], but fails to expressly discloses wherein the first and the second transistors are p-channel field effect transistors (FETs).
Bhuiyan discloses wherein the first and the second transistors are p-channel field effect transistors (FETs) (see paragraph 0016).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Bhuiyan’s teaching of a method including supplying a first supply voltage to a host interface during a first mode of operation of a non-volatile memory and supplying a second supply voltage to the host interface in response to a transition from the first mode of operation to a second mode of operation of the non-volatile memory, into Breakstone’s teaching of a storage drive including a plurality of storage devices configured to store and retrieve data responsive to operations received over Peripheral Component Interconnect Express (PCIe) interfaces, a PCIe switch circuit communicatively coupled to the PCIe interfaces of the storage devices and configured to receive over a host connector the operations issued by a host system, for the ability/benefit of having multiple voltage domains in a portable device to reduce power consumption of the portable electronic device, such as by using a reduced supply voltage for certain portions of an integrated circuit of the device that are configured to operate using the reduced supply voltage.
18. As per claim 15, Breakstone discloses “The electronic device of claim 14” [See rejection to claim 14 above], but fails to expressly discloses wherein the first type indicates an Embedded MultiMedia Card (eMMC) storage device and the second type indicates a Non-Volatile Memory Express (NVMe) storage device.
Bhuiyan discloses wherein the first type indicates an Embedded MultiMedia Card (eMMC) storage device and the second type indicates a Non-Volatile Memory Express (NVMe) storage device (see paragraph 0022).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Bhuiyan’s teaching of a method including supplying a first supply voltage to a host interface during a first mode of operation of a non-volatile memory and supplying a second supply voltage to the host interface in response to a transition from the first mode of operation to a second mode of operation of the non-volatile memory, into Breakstone’s teaching of a storage drive including a plurality of storage devices configured to store and retrieve data responsive to operations received over Peripheral Component Interconnect Express (PCIe) interfaces, a PCIe switch circuit communicatively coupled to the PCIe interfaces of the storage devices and configured to receive over a host connector the operations issued by a host system, for the ability/benefit of having multiple voltage domains in a portable device to reduce power consumption of the portable electronic device, such as by using a reduced supply voltage for certain portions of an integrated circuit of the device that are configured to operate using the reduced supply voltage.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following reference teaches of a method including supplying a first supply voltage to a host interface during a first mode of operation of a first non-volatile memory and supplying a second supply voltage to the host interface in response to a transition from the first mode of operation to a second mode of operation of a second non-volatile memory: US Pat. # 11,182,325 (Frey).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-15 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181
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