Prosecution Insights
Last updated: April 19, 2026
Application No. 18/703,375

DISPLAY SUBSTRATE AND DISPLAY APPARATUS

Non-Final OA §103
Filed
Apr 22, 2024
Examiner
LAMB, CHRISTOPHER RAY
Art Unit
2622
Tech Center
2600 — Communications
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
3 (Non-Final)
51%
Grant Probability
Moderate
3-4
OA Rounds
3y 2m
To Grant
60%
With Interview

Examiner Intelligence

Grants 51% of resolved cases
51%
Career Allow Rate
348 granted / 678 resolved
-10.7% vs TC avg
Moderate +9% lift
Without
With
+9.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
40 currently pending
Career history
718
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
55.1%
+15.1% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 678 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 December 2025 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 4-5, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0179270) in view of Cui et al. (US 10,879,330). Regarding claim 1: Chen discloses: Claim 1 Chen 1. (Currently amended) A display substrate, comprising: a display region, wherein: Fig. 1 the display region comprises a base substrate and a plurality of pixel circuits, a plurality of data lines and a plurality of data compensation units arranged on the base substrate; Shown in Fig. 1, where 11 are rows of pixel circuits, and Fig. 13, where 31 are data lines and 30 are data compensation units, as per paragraphs 83-84; the base substrate is not labeled but is shown in, e.g., Fig. 3 at least one of the plurality of data lines is electrically connected to the plurality of pixel circuits arranged in a first direction, and is electrically connected to at least one data compensation unit of the plurality of data compensation units; Paragraphs 83-84 at least one row of pixel circuits is provided between at least two adjacent data compensation units arranged in the first direction; and Not true in Chen -- columns of pixel circuits are between adjacent data compensation units instead the display region comprises a middle region, a left region and a right region along a second direction, data lines of the plurality of data lines in the middle region are not connected to the data compensation units; data lines of the plurality of data lines in the left region are connected to the data compensation units; and data lines of the plurality of data lines in the right region are connected to the data compensation units. The middle is AA11; AA12 are the left and right regions; as seen in the figure the data compensation units are only in the left and right regions Therefore Chen does not disclose: "at least one row of pixel circuits is provided between at least two adjacent data compensation units arranged in the first direction" Cui discloses: at least one row of pixel circuits is provided between at least two adjacent data compensation units arranged in the first direction (e.g., Fig. 7, where 103 are the data compensation units and 102 are the pixels; as can be seen there is a row of pixels between every data compensation unit adjacent in the first direction).1 It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Chen the elements taught by Cui. The rationale is as follows: Chen has one kind of data compensation unit. Cui shows an alternate structure for one, used in the same environment, for the same purpose, and achieving the same results, that one of ordinary skill in the art could have substituted with predictable results. Regarding claim 2: Chen in view of Cui discloses: the plurality of pixel circuits of the display region are arranged in a plurality of rows and a plurality of columns, the plurality of pixel circuits arranged in the first direction are a column of pixel circuits, and the plurality of pixel circuits arranged in a second direction are a row of pixel circuits; the first direction is intersected with the second direction (Chen Fig. 1). Regarding claim 4: Chen in view of Cui discloses: wherein the at least one data line is electrically connected to the plurality of data compensation units arranged in the first direction (Cui Fig. 7). Regarding claim 5: Chen in view of Cui discloses: wherein the plurality of data compensation units arranged in the second direction are one row of data compensation units; the at least one data line is electrically connected with the plurality of data compensation units in at least one row of data compensation units; the second direction is intersected with the first direction (Cui Fig. 7, where again Fig. 5 could be relied upon for a single row). Regarding claim 15: Chen in view of Cui discloses: A display apparatus, comprising the display substrate according to claim 1 (as discussed in the rejection of claim 1). Regarding claim 18: All elements positively recited have already been identified with respect to earlier rejections. No further elaboration is necessary. Claim(s) 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Cui, and further in view of Li et al. (US 2018/0190946) Regarding claim 6: Chen in view of Cui discloses a display substrate as discussed above. Chen in view of Cui does not disclose: “wherein the display region is a circular region.” Li discloses: wherein the display region is a circular region (e.g., Fig. 3; paragraph 31). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Chen in view of Cui the elements taught by Li. The rationale is as follows: Chen, Cui and Li are directed to the same field of art. Li discloses there can be all sorts of shapes, improving usability. This is a known improvement one of ordinary skill in the art could have included with predictable results. Regarding claim 19: All elements positively recited have already been identified with respect to earlier rejections. No further elaboration is necessary. Claim(s) 7-8, 16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Cui, and further in view of Xin et al. (US 2020/0227488) Regarding claim 7: Chen in view of Cui discloses a display substrate as discussed above. Chen in view of Cui does not disclose: "the display region comprises: a first display region and a second display region, the first display region is located at at least one side of the second display region; the plurality of pixel circuits of the display region comprises a plurality of first pixel circuits and a plurality of second pixel circuits located in the first display region; the first display region further comprises a plurality of first light emitting elements; the second display region further comprises a plurality of second light emitting elements; and at least one first pixel circuit of the plurality of first pixel circuits is electrically connected to at least one first light emitting element of the plurality of first light emitting elements, and at least one second pixel circuit of the plurality of second pixel circuits is electrically connected to at least one second light emitting element of the plurality of second light emitting elements." Xindiscloses: the display region comprises: a first display region and a second display region (e.g., Fig. 1: 110 and 120), the first display region is located at at least one side of the second display region (in Fig. 1 it is above it but depending on the orientation this could be “the side”); the plurality of pixel circuits of the display region comprises a plurality of first pixel circuits and a plurality of second pixel circuits located in the first display region (there’s a pixel circuit for each pixel shown in Fig. 1); the first display region further comprises a plurality of first light emitting elements (Fig. 1); the second display region further comprises a plurality of second light emitting element (Fig. 1)s; and at least one first pixel circuit of the plurality of first pixel circuits is electrically connected to at least one first light emitting element of the plurality of first light emitting elements, and at least one second pixel circuit of the plurality of second pixel circuits is electrically connected to at least one second light emitting element of the plurality of second light emitting elements (again, there is a pixel circuit for each pixel in the figure, and they can be connected as per the data line connections shown in Fig. 1). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Chen in view of Cui the elements taught by Xin. The rationale is as follows: Chen, Cui, and Xin are directed to the same field of art. Xin discloses two regions with different light emitting elements allow a higher-transmittance region that has a sensor (e.g., paragraph 21). This is a known improvement that one of ordinary skill in the art could have included with predictable results. Regarding claim 8: Chen, etc., discloses: wherein a length of an active layer of a drive transistor of at least one second pixel circuit along the first direction is smaller than a length of an active layer of a drive transistor of at least one first pixel circuit along the first direction (Xi paragraph 30). Regarding claim 16: Chen, etc., discloses: a sensor located on a side of a non-display surface of the display substrate (Xin paragraph 46), wherein the display region comprises: a first display region and a second display region, the first display region is located at at least one side of the second display region; and wherein an orthographic projection of the sensor on the display substrate is at least partially overlapped with the second display region of the display substrate (as seen in, e.g., Xin Fig. 8, where areas 120 and 110 are the two regions). Regarding claim 20: All elements positively recited have already been identified with respect to earlier rejections. No further elaboration is necessary. Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Cui, and further in view of Kwak et al. (US 2021/0036087) Regarding claim 9: Chen in view of Cui discloses a display substrate as discussed above. Chen in view of Cui discloses: wherein the data compensation unit comprises: a first compensation electrode plate and a second compensation electrode plate, an orthographic projection of the first compensation electrode plate on the base substrate is at least partially overlapped with an orthographic projection of the second compensation electrode plate on the base substrate (shown in Cui Fig. 9: C1 and C2); the first compensation electrode plate is electrically connected with the data line (it is connected to a data line as per Cui Fig. 6 – it doesn’t show which plate is connected here but it has to be one of them). Chen in view of Cui does not disclose: “the second compensation electrode plate is electrically connected with a first signal line.” Kwak discloses: the second compensation electrode plate is electrically connected with a first signal line (paragraph 174, where the power line is the “signal line” – note that another electrode is connected to the data line as per paragraph 170). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Cui the elements taught by Kwak. The rationale is as follows: Chen, Cui and Kwak are directed to the same field of art. Although Cui discloses that it might be a capacitor and has two plates, it doesn’t say what the second side is connected to. Kwak discloses this could be the power line (“signal line” of the claims). This is a known improvement one of ordinary skill in the art could have included with predictable results. Regarding claim 10: Chen, etc., discloses: wherein the first signal line comprises a first power supply line (Kwak paragraph 174 as discussed). Regarding claim 11: Chen, etc. discloses: in a direction perpendicular to the display substrate, the display region comprises: a base substrate, and a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the base substrate (as discussed below); the semiconductor layer at least comprises: active layers of transistors of the plurality of pixel circuits (Kwak Fig. 4: A3); the first conductive layer at least comprises: gate electrodes of transistors of the plurality of pixel circuits (Kwak Fig. 4: GE1), first capacitor electrode plates of storage capacitors of the plurality of pixel circuits (Kwak Fig. 4: CE1); the second conductive layer at least comprises: second capacitor electrode plates of the storage capacitors of the plurality of pixel circuits (Kwak Fig. 4: CE2); the third conductive layer at least comprises a plurality of connection electrodes (Kwak Fig. 4: 167); the fourth conductive layer at least comprises: the plurality of data lines(Kwak Fig. 4: 177); and the first compensation electrode plate and the second compensation electrode plate of the data compensation unit are located in different conductive layers among the first conductive layer to the fourth conductive layer (follows from the position of the electrode plates in Kwak Fig. 9, where they are above layers 111, 112, 113, etc., in Fig. 9, and as seen in Fig. 4 these conductive layers are similarly positioned). Regarding claim 12: Cui in view of Kwak discloses: wherein the first compensation electrode plate is located in the first conductive layer and the second compensation electrode plate is located in the second conductive layer; or, the first compensation electrode plate is located in the second conductive layer, and the first compensation electrode plate is located in the first conductive layer (from Kwak Fig. 9 the first, plate, connected to the data line, is 520, which is above layer 112, in Fig. 4 this is where CE2 is so this is the second conductive layer, whereas another plate is above layer 11 so this is the first conductive layer). Response to Arguments Applicant’s arguments, see page 7, filed 26 December 2025, with respect to the 35 USC 112 rejections have been fully considered and are persuasive. The 35 USC 112 rejections of the claims has been withdrawn. Applicant also (pages 8+) argued with Cui. This was used in an older Office Action to reject the independent claims. The Examiner agrees that Cui does not teach the new elements of these claims, but Chen has now been relied upon as above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER RAY LAMB whose telephone number is (571)272-5264. The examiner can normally be reached 8:30-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER R LAMB/ Primary Examiner, Art Unit 2622 1 Alternatively Fig. 5 of Cui can be relied upon, where they are clearly in rows between rows of pixels. They are not connected to the data lines in this figure but this follows from Chen.
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Prosecution Timeline

Apr 22, 2024
Application Filed
May 02, 2025
Non-Final Rejection — §103
Aug 05, 2025
Response Filed
Sep 25, 2025
Final Rejection — §103
Dec 26, 2025
Request for Continued Examination
Jan 14, 2026
Response after Non-Final Action
Jan 23, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
51%
Grant Probability
60%
With Interview (+9.1%)
3y 2m
Median Time to Grant
High
PTA Risk
Based on 678 resolved cases by this examiner. Grant probability derived from career allow rate.

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