DETAILED ACTION
This office action is in response to the application filed on 04/22/2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Drawing
The drawing submitted on 04/22/2024 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/22/2024 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-12, 14-20are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Sun et al. (NPL_ Modified LLC resonant converter with secondary paralleled bidirectional switch for applications with hold-up time requirement, hereinafter Sun).
Claim 1, Sun teaches a power converter (e.g., see Fig. 1-5) comprising:
a first voltage input comprising a first input terminal and a second input terminal (e.g., the upper and lower terminals of Uin, see Fig. 2, 4-5); a first switching element (e.g., Q1) and a second switching element (e.g., Q2) coupled in series across the first voltage input, each of the first and second switching elements having a conducting state and a non-conducting state (e.g., corresponding On/Off state of Q1 and Q2, see Fig. 2, 4); a resonant circuit coupled to the first and second switching elements and comprising: a first inductor (e.g., Lr); a first winding of a transformer (e.g., the primary winding of T, see Fig. 2, 4-5); and one or more resonant capacitors (e.g., Cr); an output circuit comprising: a voltage output (e.g., Uo); one (e.g., the secondary winding of T) or more second windings coupled to the voltage output and inductively coupleable to the first winding (e.g., see Fig. 2, 4-5); a plurality of switching devices (e.g., D1, D2) coupled to the voltage output and to the one or more second windings and configured to supply an output voltage to the voltage output in response to a current flowing through at least one switching device of the plurality of switching devices and through at least one of the one or more second windings (e.g., see Fig. 2, 4-5); and a switch assembly (e.g., the circuit comprising S5, S6) coupled to the one or more second windings and having a conducting state and a non-conducting state (e.g., see Fig. 2, 4-5); and a controller (e.g., a control circuit generating the gate control signals of S1-S6 is implicitly taught, see Fig. 2, 4-5) coupled to the switch assembly and configured to: control the switch assembly into the conducting state to cause a current flowing through the output circuit to flow through the one or more second windings without flowing through the plurality of switching devices (e.g., during t0-t2, see Fig. 4, 5a, 5b, 5c).
Claim 2, Sun teaches the limitations of claim 1 as discussed above. It further teaches that wherein the controller is further configured to control the switch assembly into the non-conducting state to cause the current flowing through the output circuit to flow through the one or more second windings and through the plurality of switching devices to generate a voltage at the voltage output (e.g., during t3-t4, see Fig. 4, 5d).
Claim 3, Sun teaches the limitations of claim 2 as discussed above. It further teaches that wherein the controller is further configured to perform a hold-up time procedure, the hold-up time procedure (e.g., Section 2.2, Operation during the hold-up time, see Col. 2 Para 2, page 399, Fig. 1, 2) configured to cause the controller to: control one of the first and second switching elements into the conducting state for a first period of time (e.g., S1&S4 being ON during t1-t5); and control the switch assembly into the conducting state for a second period of time (e.g., S5 being ON during t1-t2 and/or S6 being ON during t3-t5); wherein the first period of time is longer than the second period of time (e.g., see Fig. 4).
Claim 4, Sun teaches the limitations of claim 3 as discussed above. It further teaches that wherein the second period of time is less than half of the first period of time (e.g., see Fig. 4).
Claim 5, Sun teaches the limitations of claim 3 as discussed above. It further teaches that, wherein a beginning of the second time period occurs within the first time period after a delay period (e.g., S6 turned ON at t3 after delay when S1&S4 turned ON at t1, see Fig. 4).
Claim 6, Sun teaches the limitations of claim 3 as discussed above. It further teaches that further comprising: an AC-DC converter comprising a second voltage input (e.g., AC line input, see Col. 2 Para 2, page 399, Fig. 1) and coupled to the first voltage input (e.g., Uin being the voltage across Cb generated by AC line input see Col. 2 Para 2, page 399, Fig. 1, 2);
wherein the controller is further configured to perform the hold-up time procedure in response to a detection of a loss of input energy on the second voltage input (e.g., detecting or sensing or monitoring the loss of input energy on the AC voltage input causing Uin decreasing is implicitly taught in order for the controller to enterer the PS control mode of Operation during the hold-up time in response to Uin decreasing after the AC line input dropping out, see Section 2.2, Col. 2 Para 2, page 399, Fig. 1, 2).
Claim 7, Sun teaches the limitations of claim 6 as discussed above. It further teaches that wherein the controller is further configured to detect the loss of input energy on the second voltage input (e.g., detecting or sensing or monitoring the loss of input energy on the AC voltage input causing Uin decreasing is implicitly taught in order for the controller to enterer the PS control mode of Operation during the hold-up time in response to Uin decreasing after the AC line input dropping out, see Section 2.2, Col. 2 Para 2, page 399, Fig. 1, 2).
Claim 9, Sun teaches the limitations of claim 6 as discussed above. It further teaches that further comprising a capacitor (e.g., Cb) coupled between the first voltage input and the AC-DC converter (e.g., see Fig. 1).
Claim 10, Sun teaches the limitations of claim 1 as discussed above. It further teaches that wherein the switch assembly comprises a pair of MOSFETs (e.g., S5, S6) serially coupled together; and wherein the pair of MOSFETs is coupled in parallel with the one or more second windings (e.g., see Fig. 2).
Claim 11, Sun teaches the limitations of claim 1 as discussed above. It further teaches that wherein the resonant circuit and the first and second switching elements form a resonant half-bridge LLC series converter (e.g., Modified LLC resonant converter, see Title, Fig. 2).
Claim 12, Sun teaches the limitations of claim 1 as discussed above. It further teaches that wherein the output circuit comprises a full-wave rectifier (e.g., id1, id2, both positive and negative half cycles of the full wave received from the secondary winding are being rectified by D1 and D2 respectively, see Fig. 2, 4).
For method claims 14-20, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103(a) as being unpatentable over Sun et al. (NPL_ Modified LLC resonant converter with secondary paralleled bidirectional switch for applications with hold-up time requirement, hereinafter Sun), in view of Zhu (US Patent or PG Pub. No. 20180074136, hereinafter ‘136).
Claim 8, Sun teaches the limitations of claim 7 as discussed above. Sun further teaches that an AC-DC converter comprising a second voltage input (e.g., the AC line input, see Col. 2 Para 2, page 399) and coupled to the first voltage input (e.g., Uin being the voltage across Cb generated by AC line input see Col. 2 Para 2, page 399, Fig. 1, 2); wherein the controller is further configured to perform the hold-up time procedure in response to a loss of input energy on the second voltage input (e.g., entering the PS control mode of Operation during the hold-up time in response to Uin decreasing after the AC line input dropping out, see Col. 2 Para 2, page 399, Fig. 1, 2).
Sun does not explicitly disclose that wherein the controller, in being configured to detect the loss of input energy, is configured to: sense, via a sensor coupled to the second voltage input, a voltage on the second voltage input; compare the sensed voltage to a threshold value; and detect the loss of input energy based on the sensed voltage being less than the threshold value.
‘136 discloses AC power loss detection (e.g., see Abstract; Fig. 1-2). It further discloses that a detection the loss of input energy, to sense, via a sensor coupled to the second voltage input, a voltage (e.g., the voltage at 160) on the second voltage input; compare the sensed voltage to a threshold value (e.g., sept 215, see [0039], Fig. 2); and detect the loss of input energy based on the sensed voltage being less than the threshold value (e.g., Step 220, see [0041], Fig. 2).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Sun by including the AC power loss detection as taught by ‘136 in order of being able to reduce the rate at which a false alternating current (“AC”) loss alarming signal (e.g., see Abstract).
Claim 13 is rejected under 35 U.S.C. 103(a) as being unpatentable over Sun et al. (NPL_ Modified LLC resonant converter with secondary paralleled bidirectional switch for applications with hold-up time requirement, hereinafter Sun), in view of Hwang et al. (US Patent or PG Pub. No. 7660133, hereinafter ‘133).
Claim 13, Sun teaches the limitations of claim 1 as discussed above. Sun further teaches that wherein the plurality of switching devices comprises: a first switching device coupled to a first terminal of a first winding of the one or more second windings; and a second switching device coupled to a first terminal of a second winding of the one or more second windings; wherein a second terminal of the first winding is coupled with a second terminal of the second winding (e.g., see Fig. ).
Sun does not explicitly disclose that the first switching device is a first MOSFET, and the second switching device is a second MOSFET.
‘133 discloses an LLC converter with a synchronous rectifier circuit at the secondary side of the transformer (e.g., 16, see Abstract; Fig. 1-4). It further discloses that the synchronous rectifier circuit having the plurality of switching devices comprises: a first switching device (e.g., Q3) coupled to a first terminal of a first winding of the one or more second windings; and a second switching device (e.g., Q4) coupled to a first terminal of a second winding of the one or more second windings (e.g., see Fig. 2, 4); wherein a second terminal of the first winding is coupled with a second terminal of the second winding (e.g., see Fig. 2, 4), and further teaches that the first switching device is a first MOSFET, and the second switching device is a second MOSFET (e.g., Q3, Q4, see Fig. 2, 4).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Sun by including the MOSFET based synchronous rectifier at the secondary side of the transformer as taught by ‘133 in order of being able to provide a LLC converter having high efficiency (e.g., see col. 1 lines 39-40, col. 9 lines 19-20 ).
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
