Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the application filed on 04/22/2024.
Drawing
The drawings filed on 04/22/2024 are acceptable.
Claims 1-8 are pending and have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/22/2024 is in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly
indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa et al. (EP 2242179 A1), herein ‘Ishikawa.
In re to claim 1, Ishikawa disclose a semiconductor device (i.e. fig. 9) comprising: an inverter circuit (i.e. fig. 9, see p. [0025]) including a first switching element and a second switching element connected in series (i.e. power modules 25 are connected in series, see fig. 9); a first input terminal being an external connection terminal connected to one main electrode of the first switching element; a second input terminal being an external connection terminal connected to one main electrode of the second switching element (i.e. the external connections to the gate of the power modules 25); an output terminal being an external connection terminal connected to a connection node between the first switching element and the second switching element (i.e. to the nodes /connections 53 and 51); a first main current path being a current path from the first input terminal to the output terminal via the first switching element (i.e. the upper power module 25); a second main current path being a current path from the output terminal to the second input terminal via the second switching element (i.e. the upper power module 25); a first gate resistance connected to the gate electrode of the first switching element (i.e. resistance 23 connected to the upper power module 25); and a second gate resistance connected to the gate electrode of the second switching element (i.e. resistance 23 connected to the lower power module 25), wherein On-voltage of the second switching element is lower than On-voltage of the first switching element (i.e. the high-voltage upper power model 25 and the low-voltage lower power model 25, see ps. [0025-0026 and 0030]), switching speed of the second switching element is lower than switching speed of the first switching element (i.e. the switching speed of the power switch or upper switch is higher than the lower switch that is grounded). Except, Ishikawa fail to explicitly disclose that wiring impedance of the second main current path is higher than wiring impedance of the first main current path, and a resistance value of the second gate resistance is lower than a resistance value of the first gate resistance. However, Ishikawa disclose the claimed invention except for the specific value of the resistance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement an appropriate impedance/resistance in the current paths of the gates of a lower module, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re to claim 2, Ishikawa disclose the semiconductor device (i.e. fig. 9) according to claim 1, further comprising: a first diode (i.e. upper diode 22) connected in antiparallel to the first switching element (i.e. the upper power module 25); and a second diode (i.e. upper diode 22) connected in antiparallel to the second switching element (i.e. the lower power module 25), wherein the On-voltage of the second diode is lower than the on-voltage of the first diode (i.e. the high-voltage upper power model 25 and the low-voltage lower power model 25, see ps. [0025-0026 and 0030]),.
In re to claim 3, Ishikawa disclose the semiconductor device (i.e. fig. 9) according to claim 1. Except, Ishikawa fail to explicitly disclose that wherein at least one of the first gate resistance and the second gate resistance is an external resistance externally connected to an external connection terminal connected to the gate electrode of the first switching element or the second switching element. However, Ishikawa discloses the claimed invention except for resistances being integrated with in the power semiconductor chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to assemble the resistances external to the semiconductor switching chip, since it has been held that making an old device portable or movable without producing any new and unexpected result involves only routine skill in the art. In re Lindberg, 93 USPQ 23 (CCPA 1952).
In re to claim 4, Ishikawa disclose the semiconductor device (i.e. fig. 9) according to claim 1, wherein at least one of the first gate resistance and the second gate resistance (i.e. resistances 23) is a built-in resistance built into a chip of the first switching element or the second switching element (i.e. the lower and upper semiconductor chips 25, see fig. 9).
In re to claim 5, Ishikawa disclose the semiconductor device (i.e. fig. 9) according to claim 1 or 2, wherein at least one of the first gate resistance and the second gate resistance is a resistance of internal wiring connecting the gate electrode of the first switching element or the second switching element and an external connection terminal to each other (i.e. the lower and upper resistances within the lower and upper semiconductor switching chips 25, see fig. 9).
In re to claim 6, Ishikawa disclose the semiconductor device (i.e. fig. 9) according to claim 2. Except, Ishikawa fail to explicitly disclose that wherein at least one of the first gate resistance and the second gate resistance is an external resistance externally connected to an external connection terminal connected to the gate electrode of the first switching element or the second switching element. However, Ishikawa discloses the claimed invention except for resistances being integrated with in the power semiconductor chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to assemble the resistances external to the semiconductor switching chip, since it has been held that making an old device portable or movable without producing any new and unexpected result involves only routine skill in the art. In re Lindberg, 93 USPQ 23 (CCPA 1952).
In re to claim 7, Ishikawa disclose the semiconductor device (i.e. fig. 9) wherein at least one of the first gate resistance and the second gate resistance (i.e. resistances 23) is a built-in resistance built into a chip of the first switching element or the second switching element (i.e. the lower and upper semiconductor chips 25, see fig. 9).
In re to claim 8, Ishikawa disclose the semiconductor device (i.e. fig. 9) to claim 2, wherein at least one of the first gate resistance and the second gate resistance is a resistance of internal wiring connecting the gate electrode of the first switching element or the second switching element and an external connection terminal to each other (i.e. the lower and upper resistances within the lower and upper semiconductor switching chips 25, see fig. 9). .
Remarks
The examiner has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
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/YEMANE MEHARI/Primary Examiner, Art Unit 2838