DETAILED ACTION
1. This office action is in response to RCE communication filed on 07/02/2026. Claims 1, 13, 14 and 15 have been amended. Claims 1-15 are pending on this application.
Response to Arguments
2. Applicant’s arguments with respect to claims 1, 13 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Burns U.S. patent No. 6,445,325 in view of Li et al. U.S. patent No. 8,581,766.
Fig. 2 of Burns discloses a digital-to-analog converter form by switching resistor network; and a tap to provide reference voltage potential to one of the node of resistor network.
Fig. 3 of Burns discloses a plurality of taps 152…158 to provide reference voltage potential to plurality of nodes of resistor network.
Fig. 6 of Burn discloses non-linearity ramp output signal of digital-to-analog converter.
Regarding claim 1. Fig. 2 of Burns discloses a digital-to analog converter (Col. 2 lines 55-56) to generate nonlinear voltage ramp (see Fig. 6 for discloses non-linearity ramp output 270 of digital-to- analog converter), comprising: a resistor network (resistor network 52…64) comprising resistor elements electrically connected in series (52…64 connection in series between a first supply node (V1) and a second supply node (V2), circuit nodes (circuit nodes of 52…64) being formed between adjacent resistor elements (adjacent resistors of 52…64) ; electronic switches (70-82) , each beingg configured to connect one of the circuit nodes (circuit nodes of 52…64) with a switch arrangement output (68) to output a non-linear voltage ramp (see Fig. 6) and a reference voltage circuit (TAP 84; see Fig. 3 for discloses more taps 152…158) configured to supply a reference voltage (reference voltage of Tap) to one of the circuit nodes (node of resistor network 52…64) that is between two adjacent resistor elements (two adjacent resistors of 52…64); wherein an electric resistance of an ohmic path (resistance ohmic path between switches 70…82 and of nodes 52..64) between each of the electronic switches (70…82) and the one of the circuit nodes (one of nodes 52)
However, Burn discloses the electric resistance of an ohmic path between each of the electronic switches and the one of the circuit nodes (resistance ohmic path between switches 70…82 and of nodes 52…64) is at most 10% of an electric resistance of the resistor elements (resistance of resistor 52….64).
Fig. 5 of Li et al. discloses an DAC comprising: an electric resistance of an ohmic path (resistance ohm path between each switch 120 and resistor node) between each of the electronic switches (each of switches 120) and the one of the circuit nodes (resistor nodes) is at most 10% of an electric resistance of the resistor elements (Col. 4 lines 52-55).
Burns and Li et al. are common subject matter of resistor network for DAC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate the of Li et al. into Burns for the purpose of providing that the switches may have on resistances within other ranges of RON such as the switches 120 may have on resistances within a range of 10% or 20% of RON (Col. 4 lines 52-55 of Li et al.).
Regarding claim 2. Burns and Li et al. applied to claim 1 above, Fig. 5 of Li et al. further discloses wherein the resistor network (resistor network of 104) comprises further resistor element (RDL0…RDL(NL-1)) and each further resistor element (each of RDL0…RDL(NL-1)) is electrically connected between one of the electronic switches (120) and one of the circuit nodes (nodes of RL0…RL(NL-1).
Regarding claim 3. Burns and Li et al. applied to claim 1 above, Fig. 2 of Burns further discloses wherein each of the electronic switches (70…82) is directly connected to one of the circuit nodes (nodes of 52…82).
Regarding claim 4. Burns and Li et al. applied to claim 1 above, Fig. 2 of Burns further comprising a ramp control circuit (Fig. 1 {16}) configured to close and open the electronic switches (70…82) in a predefined order (see Fig. 3 for discloses predefined order of selection 102…108).
Regarding claim 5. Burns and Li et al. applied to claim 1 above, Burns further discloses the voltage ramp generator (Fig. 2) according to wherein the ramp control circuit (Fig. 1{106)) is configured to close one of the electronic switches (one of 70…82) at a time (a time for each switch 70…82).
Regarding claim 6. Burns and Li et al. applied to claim 4 above, Fig. 2 of Burns further discloses wherein the ramp control circuit (16 in Fig. 1) is configured to control the electronic switches (70…82) at different switching rates (see Fig. 6 and Fig. 9 for different switching rates).
Regarding claim 7, Burns and Li et al. applied to claim 1 above, Fig. 3 of Burns further comprising an output buffer circuit (114) configured to buffer a voltage signa (112) l at the switch arrangement output (output 112 of selection of 102…110).
Regarding claim 8. Burns and Li et al. applied to claim 7 above, Fig. 3 of Burns further discloses wherein the output buffer circuit (114) comprises a programmable gain amplifier (program for unity gain of 114).
Regarding claim 9. Burns and Li et al. applied to claim 1 above, Fig. 3 of Burns further comprising at least two of the reference voltage circuits (152…158) wherein the at least two reference voltage circuits (152…156) are electrically connected to different circuits nodes of the resistor network (different nodes of series resistor network).
5. Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over by Burns and Li et al. applied to claim 1 above, in view of NA Pub. No. 2021/0118376.
Regarding claim 10, Burns and Li et al. applied to claim 1 above, does not disclose wherein the at least one reference voltage circuit comprises a voltage generation circuit configured to generate a reference voltage and a buffer circuit configured to buffer the generated reference voltage.
Fig. 7 of NA discloses a ramp voltage generator (Vgm0…Vgm1012) comprising: a resistor network connection in series (resistor network 710) and at least one reference voltage circuit (one of 710) comprises a voltage generation circuit (voltage generation circuit 720) configured to generate a reference voltage (Vc1…Vc5) and a buffer circuit (730) configured to buffer (730) the generated reference voltage (Vc1…Vc5).
Burns/Li et al. and NA are common subject matter of resistors network for voltage reference generator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate NA into Burns/Li et al. for the purpose of providing there are provided improve the gamma voltage supply capacity and reduce the aforementioned RC delay by connecting the plurality of gamma voltage circuits to the gamma bus Gbus (paragraph 0057 of NA).
Regarding claim 11. Burns/Li et al. and Na applied to claim 10 above Fig. 7 of NA further discloses wherein the at least one voltage generation circuit (710) comprises: a resistor string (resistor string 710) comprising resistance elements electrically connected in series (resistor elements connected in series of 810) between a first auxiliary supply node (VH) and a second auxiliary supply node (VL), reference circuit nodes (nodes of Vc1…Vc5) being formed between electrically neighboring resistance elements (neighboring resistance elements of 710) ); and reference voltage switches (selection of PDEC) , each being configured to connect one of the reference circuit nodes (nodes of 710) with an input (input of 730) of the buffer circuit (730).
6. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over by Burns/Li et al and NA applied to claim 11 above, in view of Jiang et al. Pub. No. 2022/0206520.
Burns/Li et al. and NA applied to claim 11 above do not discloses a bandgap reference circuit configured to supply an auxiliary reference voltage to one of the reference circuit nodes.
Fig. 4 of Jiang et al. discloses a reference voltage generator (400) comprising: a bandgap reference circuit (220; paragraph 0031) configured to supply an auxiliary reference voltage (paragraph 0031) to one of a reference circuit nodes (one of the nodes of 302).
Burns/Li et al./NA and Jiang et al. are common subject matter of voltage reference generator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate the Jiang et al. into Burns/Li et al./NA for the purpose of providing the low noise voltage reference architecture may be based on a bandgap reference architecture (paragraph 0021 of Jiang et al.).
7. Claims 13 -15 are rejected under 35 U.S.C. 103 as being unpatentable over Swanson U.S. patent No. 6,414,619 in view of Burns U.S. patent No. 6,445,325 and further in view of Li et al. U.S. patent No. 8,581,766.
Regarding claim 13. Fig. 11A of Swanson disclose an analog-to-digital converter (Col. 3 lines 51-53), comprising: a voltage ramp generator (204; see Fig. 3A for discloses a diagram circuit of 204) that comprises a resistor network (R316-8….R316-1 in Fig. 3A) comprising resistor elements (R316-8….R316-1 in Fig. 3A) electrically connected in series between a first supply node (Top Node of R316-8 in Fig. 3A) and a second supply node (316 in Fig. 3A) being formed between neighboring resistor elements (neighboring R316-8….R316-1 in Fig. 3A); electronic switches (switches S3), each being configured to connect one of the circuit nodes (nodes of R316-8….R316-1 in Fig. 3A) with a switch arrangement output (arrangement of switches S3 for Vout in Fig. 3A); and a reference voltage circuit(300, 306) configured to supply a reference voltage (Vout1, Vout2) to one of the circuit nodes (one of the circuit nodes of R316-8….R316 in Fig. 3A); that is between two adjacent resistor elements (adjacent R316-8….R316 in Fig. 3A); and a comparator circuit (1120 in Fig. 11A) ) configured to compare two comparator input signals (two input signals of 1120) and to receive a voltage ramp signal (ramping of Vout in Fig. 3A) from the switch arrangement output (Vout in Fig. 3A) as one of the comparator input signals (one of the input signal of 1120).
However, Swanson does not disclose the switch arrangement output (Vout in Fig. 3A) is a non-linear voltage ramp; and electric resistance of an ohmic path between each of the electronic switches and the one of the circuit nodes (resistance ohmic path between switches 70…82 and of nodes 52…64) is at most 10% of an electric resistance of the resistor elements (resistance of resistor 52….64).
Fig. 2 of Burns discloses a digital-to analog converter (Col. 2 lines 55-56) comprising a ramp voltage generator (resistor network and switching arrangement 66), a switch arrangement output (OUTPUT 68 is a non-linear voltage ramp (see Fig. 6 or Fig. 9).
Fig. 5 of Li et al. discloses an DAC comprising: an electric resistance of an ohmic path (resistance ohm path between each switch 120 and resistor node) between each of the electronic switches (each of switches 120) and the one of the circuit nodes (resistor nodes) is at most 10% of an electric resistance of the resistor elements (Col. 4 lines 52-55).
Swanson, Burns and Li et al. are common subject matter of switching reference resistor ladder to generate an analog output voltage; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate the non-linear ramp output of Burns into ramp output of Swanson for the purpose of providing a piecewise linear segments between such breakpoints, the breakpoint voltages can then be determined for each of the breakpoints so as to implement the desired transfer characteristics, which can be monotonic or non-monotonic (Col. 2 lines 26-31 of Burns) and further incorporate Li et al. into resistor network of Swanson for the purpose of providing that the switches may have on resistances within other ranges of RON such as the switches 120 may have on resistances within a range of 10% or 20% of RON (Col. 4 lines 52-55 of Li et al.).
Regarding claim 14. Swanson, Burns and Li et al. applied to claim 13 above, Fig. 3A of Swanson further discloses wherein the at least one voltage generation circuit (314) comprises: a resistor string (R314-8….R314-1) comprising resistance elements electrically connected in series (R316-8….R316-1) between a first auxiliary supply node (VREF) and a second auxiliary supply node (Ground), reference circuit nodes (nodes or 314) being formed between electrically neighboring resistance elements (neighboring R316-8….R316-1); and reference voltage switches (switches S2) , each being configured to connect one of the reference circuit nodes (nodes or 314) with an input (308) of a buffer circuit (306).
Regarding claim 15. Fig. 3A and Fig. 11A of Swanson discloses a solid-state imaging device (the citation “solid-state imaging device” has not been given patentable weight because it has been held that a preample is denied the effect of a limitation where the claim is draw to a structure and the portion of the claim following the preample is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (ccpa 1951)), comprising: a voltage ramp generator (voltage ramping of Vout in Fig. 3A by ramp up or ramp down of resistor ladder R316-8….R316-1) that comprises a resistor network (R316-8….R316) comprising resistor elements (R316-8….R316-1) electrically connected in series (series of R316-8….R316) between a first supply node (top node of R3168) and a second supply node (316), circuit nodes (nodes of R316-8….R316-1) being formed between adjacent resistor elements (adjacent R316-8….R316-1), electronic switches (switches S3), each (S3) being configured to connect one of the circuit nodes (nodes of R316-8….R316-1) with a switch arrangement output (S3 arrangement output ), and a reference voltage circuit (300, 312) configured to supply a reference voltage (Vout1, Vout2) to one of the circuit nodes (one of the nodes R316-8….R316-1); and a comparator circuit (1120 in Fig. 11) configured to compare two comparator input signals (two input signals of 1120) and to receive a voltage ramp signal (ramping Vout of 204 in Fig. 3A) from the switch arrangement output (S3 arrangement output ) as one of the comparator input signals (one input of 1120).
However, Swanson does not disclose the switch arrangement output (Vout in Fig. 3A) is a non-linear voltage ramp; and electric resistance of an ohmic path between each of the electronic switches and the one of the circuit nodes (resistance ohmic path between switches 70…82 and of nodes 52…64) is at most 10% of an electric resistance of the resistor elements (resistance of resistor 52….64).
Fig. 2 of Burns discloses a digital-to analog converter (Col. 2 lines 55-56) comprising a ramp voltage generator (resistor network and switching arrangement 66), a switch arrangement output (OUTPUT 68 is a non-linear voltage ramp (see Fig. 6 or Fig. 9).
Fig. 5 of Li et al. discloses an DAC comprising: an electric resistance of an ohmic path (resistance ohm path between each switch 120 and resistor node) between each of the electronic switches (each of switches 120) and the one of the circuit nodes (resistor nodes) is at most 10% of an electric resistance of the resistor elements (Col. 4 lines 52-55).
Swanson, Burns and Li et al. are common subject matter of switching reference resistor ladder to generate an analog output voltage; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate the non-linear ramp output of Burns into ramp output of Swanson for the purpose of providing a piecewise linear segments between such breakpoints, the breakpoint voltages can then be determined for each of the breakpoints so as to implement the desired transfer characteristics, which can be monotonic or non-monotonic (Col. 2 lines 26-31 of Burns) and further incorporate Li et al. into resistor network of Swanson for the purpose of providing that the switches may have on resistances within other ranges of RON such as the switches 120 may have on resistances within a range of 10% or 20% of RON (Col. 4 lines 52-55 of Li et al.).
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
08/13/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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