Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim status
Claims 1-2, 6-7 and 9-11 are pending; claim 1, 6 and 9 are independent. Claims 3-5, 8 and 12 have been cancelled.
Response to Arguments
Applicant's arguments filed 01/08/2026 have been fully considered but they are not persuasive.
In response to applicant’s argument that Hu view of Kim cannot teach the limitations "data signals are provided to the plurality of data lines simultaneously via the data output channels, respectively”, as recited in claims 1, 6 and 9.
However, the examiner respectfully disagrees, Hu clearly taught in fig. 3 and Paras 0072-0078, wherein the source driver 10′, provides a plurality of source driving channels to correspond to a plurality of data wires 20′ and displays the image data, according to the turned on scanning lines 40′. Para [0076] The source driver 10′ controls the pixel unit to display, according to the two adjacent scanning lines, so that the image data could be carried out with column extension according to two adjacent scanning lines 40′. Para [0077] The timing controller 50′ could transmit the image data to the source driver 10′, and turn on simultaneously at least one pair of scanning lines 40′. The source driver 10′ could control the corresponding pixel unit to produce a display, according to the control data. In fig. 8, S30 and Paras 0110-0113, wherein turning on simultaneously a plurality of scanning lines according to the control signal by the gate driver; driving respectively a pixel unit connected with the turned on scanning lines according to the extended image data signal by the source driver), so data signals are provided to the plurality of data lines simultaneously via the data output channels, respectively according to turn two or more adjacent scanning lines 40′ simultaneously.
In response to applicant’s argument that Hu view of Kim cannot teach the limitations " wherein the scan signals are generated according to clock signals, the quantity of clock signals is greater than 2, respectively”, as recited in claims 1, 6 and 9.
However, the examiner respectfully disagrees, Hu taught in fig. 4 and Para 0081, wherein the gate driver 30′ is configured to receive a first control data of the timing controller 50′ transmitted, and turn on in sequence a preset number of scanning lines 40′ in pairs, but more clarify Kim discloses in fig. 5 and Paras 0068-0072, wherein gate lines G1, G2. G3, and G4 may receive their gate scan signals simultaneously, gate lines G5, G6, G7, and G8 may receive their gate scan signals simultaneously, and, likewise, gate lines G9, G10, G11, and G12 may receive their gate scan signals simultaneously. Accordingly, for the entire array substrate under the forward scan mode for example, every four successive rows of sub-pixels arranged in order from top to bottom may be turned on simultaneously, and every four sub-pixels that spread among these four rows respectively and that are located in one same column may receive the same data signal.
In response to applicant’s argument that Hu view of Kim cannot teach the limitations wherein the providing scan signals through the plurality of scan lines and the providing data signals to the plurality of data lines simultaneously through the data chip comprises providing scan signals with a same timing through an m-th scan line and an (m+1)-th scan line in the plurality of scan lines, and providing data signals to an m-th row of sub-pixels and an (m+1)- th row of sub-pixels simultaneously through the data chip, wherein m is a positive integer less than or equal to (M-1), and m is an odd number, as recited claims 1, 6 and 9.
However, the examiner respectfully disagrees, Kim taught in figs 4-5, Paras 0033-0034 and 0070-0078, wherein Q groups of shift register units cascaded in series, one of the Q groups of shift register units cascaded in series comprising S shift register units cascaded in series, each of the S shift register units for outputting scan signals to M gate lines, and S×M clock signal lines, M clock signal lines of which is coupled to one of the S shift register units in each of the Q groups of shift register units, Q, S and M are integer, S≥2, M≥2; wherein each of the S shift register units comprises a control circuit configured to output a control signal, M buffer circuits coupled to the control circuit, and S×M buffer circuits coupled to the S×M clock signal lines for sequentially providing S×M clock signals respectively in one group of the Q groups of shift register units cascaded in series, wherein each of the M buffer circuits is configured to be controlled by the control signal and one of the M clock signals provided by the M clock signal lines to output a scan signal to a gate line of the M gate lines. [0034] Optionally, the S×M clock signals sequentially from 1.sup.st clock signal to the S×M-th clock signal are provided with a time-delay between any pair of subsequent clock signals. [0069] the output signals of the first system clock signal terminal CLK1, the second system clock signal terminal CLK2, the third system clock signal terminal CLK3, and the fourth system clock signal terminal CLK4 may be the same as one another. The fifth system clock signal terminal CLK5, the sixth system clock signal terminal, the seventh system clock signal terminal tCLK7, and the eighth system clock signal terminal CLK8 may output the same signals. Likewise, the output signals of the ninth system clock signal terminal CLK9, the tenth system clock signal terminal CLK10, the eleventh system clock signal terminal CLK11, and the twelfth system clock signal terminal CLK12 may be the same as each other. [0078] The clock signal terminals CK of the first buffer circuit BF_1 and the second buffer circuit BF_2 in the fourth shift register unit 104 may be coupled to a seventh system clock signal terminal CLK7 and an eighth system clock signal terminal CLK8, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-7 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 2021/0158735), and further in view of Kim (US 2020/0258463).
Regarding claim 1, Hu teaches a display driving method, applied to a display device (fig. 8), wherein the display device comprises a base substate (fig. 3, the main body of a display panel) a plurality of scan lines (fig. 3, a plurality of scanning lines 40′) and a plurality of data lines arranged on the base substrate (fig. 3, a plurality of data wires 20′ and Para 0058),
the display substrate further comprises a data chip (fig. 3, a source drive 10′), output terminals of data output channels of the data chip are directly connected to the plurality of data lines, respectively, the data output channels are in one-to-one correspondence to the plurality of data lines, and data signals are provided to the plurality of data lines simultaneously via the data output channels, respectively (fig. 3 and Paras 0072-0074, wherein the source driver 10′, provides a plurality of source driving channels to correspond to a plurality of data wires 20′ and displays the image data, according to the turned on scanning lines 40′. In fig. 8, S30 and Paras 0110-0113, wherein turning on simultaneously a plurality of scanning lines according to the control signal by the gate driver; driving respectively a pixel unit connected with the turned on scanning lines according to the extended image data signal by the source driver),
wherein the method comprises:
receiving an image display instruction (fig. 8, S10, S20 and Paras 0108-0109) ;
providing scan signals through the plurality of scan lines; and providing the data signals to the plurality of data lines simultaneously through the data chip, wherein each of the data output channels of the data chip provides a data signal to a corresponding one of the plurality of data lines (fig. 8, S30 and Paras 0110-0113, wherein turning on simultaneously a plurality of scanning lines according to the control signal by the gate driver; driving respectively a pixel unit connected with the turned on scanning lines according to the extended image data signal by the source driver);
Hu does not expressly disclose wherein the scan signals are generated according to clock signals, the quantity of clock signals is greater than 2 and wherein the quantity of clock signals is 4 groups, 8 groups or 16 groups; and wherein the quantity of the plurality of scan lines is M, and M is a positive even number; and wherein the providing scan signals through the plurality of scan lines and the providing data signals to the plurality of data lines simultaneously through the data chip comprises providing scan signals with a same timing through an m-th scan line and an (m+1)-th scan line in the plurality of scan lines, and providing data signals to an m-th row of sub-pixels and an (m+1)- th row of sub-pixels simultaneously through the data chip, wherein m is a positive integer less than or equal to (M-1), and m is an odd number.
However, Kim discloses “wherein the scan signals are generated according to clock signals, the quantity of clock signals is greater than 2”, see fig. 5 and Paras 0068-0072 and “wherein the quantity of clock signals is 4 groups, 8 groups or 16 groups”, see Paras 0033-004; and
wherein the quantity of the plurality of scan lines is M, and M is a positive even number (fig. 4 and pair of scanning lines, ex G(1), G(2); and wherein the providing scan signals through the plurality of scan lines and the providing data signals to the plurality of data lines simultaneously through the data chip comprises providing scan signals with a same timing through an m-th scan line and an (m+1)-th scan line in the plurality of scan lines, and providing data signals to an m-th row of sub-pixels and an (m+1)- th row of sub-pixels simultaneously through the data chip, wherein m is a positive integer less than or equal to (M-1), and m is an odd number, figs 4-5, Paras 0033-0034 and 0070-0078.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modified a display of Hu with applying the teaching of Kim to include clock signals divided into a plurality of groups of clock signals, wherein each of shift register units comprises a control circuit configured to output a control signal, buffer circuits coupled to the control circuit, and buffer circuits coupled to the clock signal lines for sequentially providing clock signals respectively in one group of groups of shift register units cascaded in series, wherein each of the buffer circuits is configured to be controlled by the control signal and one of the clock signals provided by the clock signal lines to output a scan signal to a gate line of the gate lines. Accordingly, for the entire array substrate under the forward scan mode for example, every four successive rows of sub-pixels arranged in order from top to bottom may be turned on simultaneously, and every four sub-pixels that spread among these four rows respectively and that are located in one same column may receive the same data signal, as a known technique to yield a predictable result.
Regarding claim 2, Hu in view of Kim teaches the method according to claim 1, wherein the plurality of scan Ines is divided into a plurality of groups along a direction for arranging the plurality of scan lines, and the quantity of scan lines in at least some of the plurality of groups is greater than 1 (fig. 3 and Para 0069, wherein the gate driver 30′ is configured to receive a first control data of the timing controller 50′, and turn on in sequence a preset number of scanning lines 40′ in pairs, Kim); and
wherein the providing scan signals through the plurality of scan lines comprises providing scan signals having a same timing to scan lines in a same group (fig. 4 and Para 0071, wherein during a preset time, the gate driver 30′ simultaneously turns on the scan lines 40′, G(1) and G(2) under the function of the control data, Kim).
Regarding claims 6 and 9, Hu teaches a display device (fig. 3), comprising:
a display substrate (fig. 3, a display panel), comprises a base substrate (fig. 3, the main body of a display panel); and sub-pixel driving circuits arranged on the base substrate (Para 0074, wherein he driving device further includes a pixel unit),
wherein a plurality of scan lines configured to provide scan signals and a plurality of data lines are arranged on the base substrate, and the scan line and the data line are connected to a corresponding sub-pixel driving circuit (fig. 3 and Paras 0060-0063, wherein the source driver 10′ is configured to drive respectively a pixel unit connected with the plurality of scanning lines);
wherein the display substrate further comprises a data chip (fig. 3, a source drive 10′), the data chip comprises data output channels, the data output channels are directly connected to the plurality of data lines, respectively, and the data output channels are in one-to-one correspondence to the plurality of data lines; wherein data signals are provided to the plurality of data lines simultaneously via the data output channels, respectively (fig. 3 and Paras 0072-0074, wherein the source driver 10′, provides a plurality of source driving channels to correspond to a plurality of data wires 20′ and displays the image data, according to the turned on scanning lines 40′. In fig. 8, S30 and Paras 0110-0113, wherein turning on simultaneously a plurality of scanning lines according to the control signal by the gate driver; driving respectively a pixel unit connected with the turned on scanning lines according to the extended image data signal by the source driver),
Hu does not expressly disclose wherein the scan signals are generated according to clock signals, the quantity of clock signals is greater than 2 and wherein the quantity of clock signals is 4 groups, 8 groups or 16 groups; and wherein the quantity of the plurality of scan lines is M, and M is a positive even number; and wherein the providing scan signals through the plurality of scan lines and the providing data signals to the plurality of data lines simultaneously through the data chip comprises providing scan signals with a same timing through an m-th scan line and an (m+1)-th scan line in the plurality of scan lines, and providing data signals to an m-th row of sub-pixels and an (m+1)- th row of sub-pixels simultaneously through the data chip, wherein m is a positive integer less than or equal to (M-1), and m is an odd number.
However, Kim discloses “wherein the scan signals are generated according to clock signals, the quantity of clock signals is greater than 2”, see fig. 5 and Paras 0068-0072 and “wherein the quantity of clock signals is 4 groups, 8 groups or 16 groups”, see Paras 0033-004; and
wherein the quantity of the plurality of scan lines is M, and M is a positive even number (fig. 4 and pair of scanning lines, ex G(1), G(2); and wherein the providing scan signals through the plurality of scan lines and the providing data signals to the plurality of data lines simultaneously through the data chip comprises providing scan signals with a same timing through an m-th scan line and an (m+1)-th scan line in the plurality of scan lines, and providing data signals to an m-th row of sub-pixels and an (m+1)- th row of sub-pixels simultaneously through the data chip, wherein m is a positive integer less than or equal to (M-1), and m is an odd number, figs 4-5, Paras 0033-0034 and 0070-0078.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modified a display of Hu with applying the teaching of Kim to include clock signals divided into a plurality of groups of clock signals, wherein each of shift register units comprises a control circuit configured to output a control signal, buffer circuits coupled to the control circuit, and buffer circuits coupled to the clock signal lines for sequentially providing clock signals respectively in one group of groups of shift register units cascaded in series, wherein each of the buffer circuits is configured to be controlled by the control signal and one of the clock signals provided by the clock signal lines to output a scan signal to a gate line of the gate lines. Accordingly, for the entire array substrate under the forward scan mode for example, every four successive rows of sub-pixels arranged in order from top to bottom may be turned on simultaneously, and every four sub-pixels that spread among these four rows respectively and that are located in one same column may receive the same data signal, as a known technique to yield a predictable result.
Regarding claims 7 and 11, Hu in view of Kim teaches the display substrate according to claim 6 and the display device according to claim 9, wherein the plurality of scan lines is divided into a plurality of groups along a direction for arranging the plurality of scan lines, the quantity of scan lines in at least some of the plurality of groups is greater than 1 (fig. 3 and Para 0069, wherein the gate driver 30′ is configured to receive a first control data of the timing controller 50′, and turn on in sequence a preset number of scanning lines 40′ in pairs, Kim), and
scan lines in a same group are connected to scan signal terminals which provide scan signals with a same timing (fig. 4 and Para 0071, wherein during a preset time, the gate driver 30′ simultaneously turns on the scan lines 40′, G(1) and G(2) under the function of the control data, Kim).
Regarding claim 10, Hu in view of Kim teaches the display device according to claim 9, wherein the display device is a field sequential liquid crystal display device, and/or the display device is a near-eye display device (Para 0002, Kim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
WU (US 2022/0334440), relates to the field of display technology, for example, an array substrate, a display panel, a display device, and a driving method.
Zhang (US 2021/0358369), related to a display panel which can reduce the interference on an image displayed by pixel units caused from pulse signals of a capacitance formed by a de-multiplex control signal output line and a data signal output line.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
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/S.E.E/Examiner, Art Unit 2625 3/21/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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