DETAILED ACTION
1. This action is in response to the amendment filed on 8/4/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
3. Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 3, and 24-31 are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US 20160072384) in view of Sato et al. (US 20090153118).
Regarding claim 1: Fan discloses a boost converter circuit (i.e. figure 1) comprising:
an input (i.e. 10) arranged to receive an input voltage (i.e. Vin);
an output (i.e. 19) arranged to generate a higher, output voltage (i.e. Vout) for powering a further circuit portion (i.e. load connect to 19);
a switching arrangement (i.e. SW) arranged to control generation of the output voltage (i.e. Vout); and
a control circuit portion (i.e. control circuit of figure 1) arranged to monitor (i.e. by 11) the input voltage (i.e. Vin) and control the switching arrangement (i.e. SW) in response to the input voltage (i.e. Vin) (i.e. ¶ 16-18).
wherein the control circuit portion (i.e. control circuit of figure 1) is arranged to control the switching arrangement (i.e. SW) to limit an output current (i.e. current to load, by controlling the switch SW) of the boost converter circuit in response to the input voltage (i.e. Vin) (i.e. ¶ 16-18);
wherein the control circuit portion (i.e. control circuit of figure 1) is arranged to control the switching arrangement (i.e. SW) to limit the output current (i.e. current to load, by controlling the switch SW) of the boost converter circuit (i.e. figure 1) based on a comparison (i.e. by 11) between the input voltage (i.e. Vin) and a reference input voltage (i.e. voltage to + terminal of 11),
but does not specifically disclose a reference input voltage derived from an unloaded voltage of the power supply.
Sato et al. disclose a power supply (i.e. figures 1-2) a reference input voltage (i.e. volage 10 to comparator 14) derived (i.e. derived by 10) from an unloaded voltage of the power supply (i.e. battery voltage 1a) (i.e. ¶ 7 and 49).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fan’s invention with the power supply as disclose by Sato et al. to providing a stable power supply controller.
Regarding claim 3: (i.e. figure 1) wherein the control circuit portion (i.e. control circuit of figure 1) comprises a comparator (i.e. 11) arranged to compare the input voltage (i.e. Vin) with a reference input voltage (i.e. Vsw) and to control the switching arrangement (i.e. SW) to limit the output current (i.e. current to load) of the boost converter circuit in response to an output (i.e. from 11) of said comparator (i.e. 11) (i.e. ¶ 16-18).
Regarding claim 24: Fan discloses (i.e. figure 1) a circuit portion comprising: the boost converter circuit (i.e. circuit of figure 1) as claimed in claim 1; and the power supply (i.e. 10).
Regarding claim 25: Fan discloses (i.e. figure 1) wherein the control circuit portion (i.e. control circuit of figure 1) controls the switching arrangement (i.e. SW) to ensure that the input voltage (i.e. Vin) does not fall below the reference input voltage (i.e. voltage to + terminal of 11) (i.e. ¶ 16-18).
Regarding claim 26: Fan discloses (i.e. figure 1) wherein the control circuit portion (i.e. control circuit of figure 1) is arranged to control the switching arrangement (i.e. SW) so as to limit the output current (i.e. current to load, by controlling the switch SW) of the boost converter circuit when the input voltage (i.e. Vin) indicates that the output current (i.e. current to load, by controlling the switch SW) is near or at a maximum value (i.e. any value of the output current) (i.e. ¶ 16-18).
Regarding claim 27: Fan discloses (i.e. figure 1) wherein the control circuit portion (i.e. control circuit of figure 1) prevents the boost converter circuit from attempting to deliver a higher current (i.e. any current output value that control by the switch SW) when the input voltage (i.e. Vin) has dropped to a value (i.e. value of the voltage input to the + terminal of comparator 11) indicating that the output current is at its maximum possible level (i.e. any level of the current output) (i.e. ¶ 16-18).
Regarding claim 28: Fan discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the boost converter circuit is arranged to estimate the unloaded voltage of the power supply.
Sato et al. disclose a power supply (i.e. figures 1-2) the converter circuit (i.e. circuit of 10) is arranged to estimate the unloaded voltage of the power supply (i.e. 1) (i.e. ¶ 11-12).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fan’s invention with the power supply as disclose by Sato et al. to have the boost converter circuit is arranged to estimate the unloaded voltage of the power supply, because it provides a stable power supply controller.
Regarding claim 29: Fan discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the boost converter circuit is arranged to directly measure the unloaded voltage of the power supply.
Sato et al. disclose a power supply (i.e. figures 1-2) the converter circuit (i.e. circuit of 10) is arranged to directly measure the unloaded voltage of the power supply (i.e. 1) (i.e. ¶ 11-12).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fan’s invention with the power supply as disclose by Sato et al. to have the boost converter circuit is arranged to directly measure the unloaded voltage of the power supply, because it provides a stable power supply controller.
Regarding claim 30: Fan discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the predetermined reference input voltage is derived from an unloaded voltage of a possible power source having a particular age.
Sato et al. disclose a power supply (i.e. figures 1-2) the predetermined reference input voltage (i.e. 10a) is derived from an unloaded voltage (i.e. 1) of a possible power source having a particular age (i.e. age of the battery 1) (i.e. ¶ 11-12).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fan’s invention with the power supply as disclose by Sato et al. to providing a stable power supply controller.
Regarding claim 31: Fan discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the predetermined reference input voltage is derived from an unloaded voltage of a possible power source when operated in particular ambient conditions.
Sato et al. disclose a power supply (i.e. figures 1-2) the predetermined reference input voltage (i.e. 10a) is derived from an unloaded voltage (i.e. voltage 1a) of a possible power source (i.e. 1) when operated in particular ambient conditions (i.e. condition of the battery 1) (i.e. ¶ 11-12).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fan’s invention with the power supply as disclose by Sato et al. to providing a stable power supply controller.
6. Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US 20160072384) in view of Sato et al. (US 20090153118) and further in view of Locascio (US 20110241625).
Regarding claim 4: Fan discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the reference input voltage is between 25% and 75% of the unloaded voltage of the power supply.
Locascio disclose a power supply (i.e. figures 2-3) comprising the reference input voltage (i.e. from 170 is .3V) is between 25% and 75% of the unloaded voltage of the power supply (i.e. from 120 is .5V) (i.e. ¶ 29-31).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fan’s invention with the power supply as disclose by Locascio to enable efficient pulses of energy to be delivered from the storage capacitor to the storage element when the boost converter circuit is turned on.
In addition, it would have been obvious to one having ordinary skill in the art at the time the invention was made to Fan’s invention to have input voltage is between 25% and 75% of an unloaded power supply voltage in order to increase the efficiency of the power supply. Since, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 5: Fan discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the reference input voltage is a predetermined reference input voltage.
Locascio disclose a power supply (i.e. figures 2-3) comprising the reference input voltage is a predetermined reference input voltage (i.e. 170) (i.e. ¶ 29-31).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fan’s invention with the power supply as disclose by Locascio to enable efficient pulses of energy to be delivered from the storage capacitor to the storage element when the boost converter circuit is turned on.
Regarding claim 6: Fan discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the predetermined reference input voltage is between 0.1 V and 2 V.
Locascio disclose a power supply (i.e. figures 2-3) comprising the predetermined reference input voltage (i.e. 170) is between 0.1 V and 2 V (i.e. ¶ 29-31).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fan’s invention with the power supply as disclose by Locascio to enable efficient pulses of energy to be delivered from the storage capacitor to the storage element when the boost converter circuit is turned on.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nguyen Tran/Primary Examiner, Art Unit 2838
