Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/26/2024 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Claim Objections
Claim 12 is objected to because of the following informalities:
Claim 12: .
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Specifically, in claims 6, the limitation “the vertical trenches are filled with a porous low-k dielectric” is unclear, inconsistent with claim 1, and not supported by the specification. The claim does not disclose an arrangement in which the vertical trenches are filled with a porous low-k dielectric in addition to the dielectric(s) that coats and seals the trenches (as cited in claims 1). It also cannot be indirectly derived from the specification how an additional dielectric layer would be applied, since the vertical trenches have already been coated and sealed by a first dielectric layer (see claim 1). The specification (see pages 11-12) is unclear in this respect. In particular, page 12 indicates the porous dielectric could potentially mean the sealing dielectric itself, however, there is nothing disclosed on how an additional dielectric material would be introduced into the already sealed trenches. Therefore, it is unclear as to whether the “porous low-k dielectric” from claim 6 is the coating and sealing dielectric from claim 1, or an additional dielectric filling layer (not supported by the specification). Claim 17 is also rejected as a dependent of claim 6.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation “…extends partially and/or continuously through the wafer”, the “and” variant renders the claim indefinite because it is unclear how one can extend partially and continuously through an object. For examination purposes, based on broadest reasonable interpretation, the examiner has interpreted this limitation as “extends partially or continuously through the wafer.” However, this also cast doubt on the scope of protection of claims 1 and 3, because it then specifies one feature (“a through-via”) as merely being optional.
Claim 11 recites the limitation "the MEMS device" and "the electronic circuit" in line 3. There is insufficient antecedent basis for this limitation in the claim as claim 11 depends on claim 1.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
The limitation “a connection pad is applied to a contact side of the wafer or wafer stack on the via region, an insulating layer, at least partially omitting the via region, and the connection pad being formed by filling the omitted region with a conductive material” renders the claim indefinite because it is unclear what the structural relationship is between the connection pad and the insulating layer. Specifically, it is unclear where the “contact side” is, how the “insulating layer” is formed or placed, and what relation the “insulating layer” has with the “connection pad” and “contact side”. As the claim reads, it is evident that essential structural language is missing. For examination purposes, based on broadest reasonable interpretation, the examiner has interpreted this limitation as “wherein an insulating layer is formed on a front side or back side of the wafer or wafer stack, at least partially omitting the via region, and a connection pad is formed by filling the omitted via region with a conductive material.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Reinmuth et al. (US8778194B2).
Regarding Claim 1:
Reinmuth discloses a method (paragraphs 10-28) for producing a via for a semiconductor component comprising at least one wafer, comprising the following steps:
(a) forming vertical trenches (Fig. 7 element 160) within the wafer (element 110), which enclose a via region (elements 150/175, paragraph 23),
(b) coating and sealing the vertical trenches with a dielectric (Fig. 5 element 172), the vertical trenches being only partially filled with the dielectric (see Fig. 5; 172 coats the side walls of the trenches and seals them at the same time), and
(c) connection of the via region (elements 150/175) to an electrical connection (Figs. 8-10 elements 180/190/130/135).
Regarding Claim 2:
Reinmuth discloses a method according to claim 1, wherein the semiconductor component (Fig. 20 element 101, paragraphs 35-37) comprises a MEMS device and/or an electronic circuit (element 201) which are operated by connecting the via region to the electrical connection (paragraph 46).
Regarding Claim 3:
Reinmuth discloses a method according to claim 1, wherein the via region (Figs. 6-10/20 elements 150/175) extends partially and/or continuously (paragraphs 42) through the wafer (elements 110 and 210).
Regarding Claim 4:
Reinmuth discloses a method according to claim 1, wherein the wafer (Fig. 20 element 110) exhibits a front (element 112) and rear side (element 111), wherein the via (elements 150/175) extends from the front side to the rear side (paragraphs 31 and 42), a MEMS device and/or an electronic circuit (element 201) is/are present on the rear side, which is/are connected to the via region (paragraph 46).
Regarding Claim 10:
Reinmuth discloses a method according to claim 1, wherein the vertical trenches (Figs. 5-10 element 160) are sealed with a dielectric (elements 172/171) and/or the vertical trenches are hermetically sealed by coating with the dielectric and/or a sealing layer is additionally applied for hermetic sealing (paragraphs 17-19 and 38), wherein the dielectric for partially filling and coating the vertical trenches and/or the sealing layer comprises silicon nitride, tetraethyl orthosilicate, silicon oxynitride and/or silicon dioxide (paragraphs 18-19).
Regarding Claim 11:
Reinmuth discloses a method according to claim 1, for providing a connection of an electrical connection (Figs. 10 and 20) for operating the MEMS device (element 201) and/or the electronic circuit (element 199) to the via region (elements 150/175), a region of the via region is connected to a conductive material or a connection opening (elements 180/190/196/135/121/131/130) is formed in a wafer of a wafer stack (elements 110/210), which is filled with a conductive material (paragraphs 11 and 23-36).
Regarding Claim 12:
Reinmuth discloses a method according to claim 1, wherein a connection pad (Fig. 8 elements 131/190) is applied to a contact side (elements 111/112) of the wafer or wafer stack (element 110) on the via region (elements 150/175), an insulating layer, at least partially omitting the via region (elements 172/124/120), and the connection pad being formed by filling the omitted region with a conductive material (paragraphs 11-23).
Regarding Claim 13:
Reinmuth discloses a method according to claim 1, wherein the via region (Figs. 5-8 elements 150/175) between the vertical trenches (element 160) is removed and filled with a metal (paragraph 25).
Regarding Claim 14:
Reinmuth discloses a method according to claim 1, wherein the semiconductor component (Figs. 10 and 20 element 100/101) exhibits a MEMS device and/or an electronic circuit (elements 199/201), wherein the MEMS device comprises an acceleration sensor, a gyroscope, a pressure sensor, a microphone, a flow sensor and/or a gas sensor and/or the electronic circuit comprises a high-frequency component, an integrated readout circuit and/or an amplifier (paragraphs 13, 33-37).
Regarding Claim 15:
Reinmuth discloses a semiconductor component (Figs. 6-10 element 100) with a via (elements 150/175) produced (paragraphs 10-28) according to a method according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7, 9, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Reinmuth et al. (US8778194B2).
Regarding Claim 5:
Reinmuth discloses a method according to claim 4, wherein the semiconductor component exhibits a cavity (Fig. 17 paragraph 37) in which a MEMS device and/or an electronic circuit (element 201) is present, wherein the cavity is within a wafer stack formed by at least two wafers (elements 110/210) and the via region extends (elements 150/175) through at least one of the two wafers (paragraph 42), wherein there is a negative pressure present in the cavity (paragraphs 19 and 38).
The examiner notes that even though Reinmuth does not explicitly disclose a negative pressure present within the cavity containing the MEMS device/electronic circuit, one of ordinary skill in the art understands that certain deposition processes (i.e., CVD and TEOS) produce a negative pressure after a sealing process has been carried out.
Regarding Claim 7:
Reinmuth discloses a method according to claim 1, wherein a negative pressure is present (paragraph 18-19) within the vertical trenches (Fig. 5 element 160) after sealing and/or these are filled with a gas before sealing (paragraphs 17-19).
The examiner notes that even though Reinmuth does not explicitly disclose a negative pressure present within the vertical trenches, one of ordinary skill in the art understands that certain deposition processes (i.e., CVD and TEOS) produce a negative pressure after a sealing process has been carried out when removing unwanted byproducts. Additionally, one of ordinary skill in the art understands that during the manufacturing process, the vertical trenches are, at least in part, filled with air and/or the CVD process can introduce gases into the trenches to be filled and then sealed.
Regarding Claim 9:
Reinmuth discloses a method according to claim 1, wherein the vertical trenches (Fig. 3 element 160) are formed by wet chemical etching processes and/or dry etching processes (paragraphs 13 and 23-24, 43-59), and/or the vertical trenches exhibit an aspect ratio of up to 50:1 and/or a depth of between 100 µm and 1000 µm (paragraphs 8, 12, and 16-20).
The examiner first notes that Reinmuth does not explicitly disclose an aspect ratio (depth/width) value or a depth range for the vertical trenches. However, Reinmuth recognizes that there is a distinct relationship between the aspect ratio of the trenches and the effectiveness of the sealing process of the trenches (paragraph 20). Furthermore, Reinmuth recognizes to decrease the mechanical stress occurred on the vias, the aspect ratio – consequently the depth – of the vertical trenches is critical (paragraph 8). The depth range and aspect ratio is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the aspect ratio – consequently the depth – as Reinmuth has identified as a result effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a depth range of 100-1000 µm, thus an aspect ratio of 50:1, in order to achieve the desired via protection by the vertical trenches, as taught by Reinmuth. MPEP 2144.05.
Regarding Claim 18:
Reinmuth discloses a method according to claim 7, wherein the vertical trenches (Fig. 5 element 160) are filled with a gas (adjunct gases) that exhibits a lower dielectric constant than the dielectric for sealing (paragraphs 17-19).
The examiner notes that even though Reinmuth does not explicitly disclose that the vertical trenches are filled with a gas/air that has a lower dielectric constant than that of the sealant, one of ordinary skill in the art understands that during the CVD/TEOS process, the vertical trenches are filled with an adjunct gas/air and there is residual gas present that is then sealed. Furthermore, one of ordinary skill in the art understands that the common adjunct gases used exhibit a lower dielectric constant than that of silicon dioxide.
Regarding Claim 19:
Reinmuth discloses a method according to claim 9, wherein Reinmuth further discloses the vertical trenches (Fig. 3 element 160) are formed by physical and/or chemical dry etching processes (paragraphs 13 and 23-24, 43-59).
Regarding Claim 20:
Reinmuth discloses a method according to claim 19, wherein Reinmuth further discloses the vertical trenches (Fig. 3 element 160) are formed by reactive ion etching and/or reactive ion deep etching (Bosch process) (paragraphs 13 and 43).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Reinmuth et al. (US8778194B2) in view of Reinmuth et al. (US 20130209672A1), hereinafter referred to "Reinmuth '672".
Regarding Claim 16:
Reinmuth discloses a method according to claim 5, but Reinmuth does not explicitly disclose where the negative pressure is a vacuum.
Reinmuth ‘672 discloses an analogous method for manufacturing a semiconductor component having a through-connection (paragraphs 33-63), wherein the method includes forming and sealing parts of the semiconductor component through the use of a vacuum. The method additionally comprises forming a MEMS device/electronic circuit (Fig. 13 element 180) in a cavity between a wafer stack (elements 105 and 190), wherein a negative pressure is present within the cavity (paragraphs 63-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the method describe in Reinmuth further in view of Reinmuth ‘672 to explicitly include where the negative pressure, present within the cavity, is a vacuum because both are directed to analogous methods. Doing so ensures the sealing of the micromechanical structure is effectively performed (Reinmuth ‘672, paragraphs 4 and 65).
Claims 6, 8, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Reinmuth et al. (US8778194B2) in view of Wu et al. (US20110291287A1).
Regarding Claim 6:
Reinmuth discloses a method according to claim 1, but does not explicitly disclose where the vertical trenches are filled with a porous low-k dielectric.
Wu, however, discloses an analogous a method for fabricating a via in a semiconductor substrate (paragraphs 2-17) wherein the vertical trenches (Figs. 5B-D elements 507/509) are filled with a porous low-k dielectric (paragraphs 46-47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Reinmuth further in view of Wu to explicitly include where the vertical trenches are filled with a porous low-k dielectric because both are directed to analogous methods for producing a via in a semiconductor device. Doing so improves the efficiency of the electrical connections in the semiconductor component (Wu, paragraph 52).
Regarding Claim 8:
Reinmuth discloses a method according to claim 1, wherein the vertical trenches (Fig. 3 elements 141/160) exhibit an opening (element 141) and, starting from a width of the opening, are widened laterally to form a widened region (element 160), that are widened laterally by at least 2 µm compared to the width of an opening (Fig. 3), and/or the opening exhibits a depth of less than 5 µm and a width of less than 2 µm (paragraphs 12-13). However, Reinmuth does not explicitly disclose a range for the width of the widened region of the trenches.
Wu discloses an analogous method for fabricating a via in a semiconductor substrate (paragraphs 2-17), wherein the vertical trenches (Figs. 5B-D elements 507/509/504) exhibit a widened region (elements w1/w2) wherein the lateral widening is less than 20 µm and/or the widened region exhibits a width of at least 10 µm (paragraphs 46-48).
The examiner first notes that Reinmuth does not explicitly disclose a range of widths/depths for the opening and the widened regions of the vertical trenches. The examiner next notes the widths and depths are a result effective variable because adjusting these values can have a direct effect on the overall manufacturing process. Specifically, the effectiveness of the sealing outcomes and the mitigation of potential parasitic capacitances. The examiner additionally notes that the widths/depths of these trenches is recognized by the prior art as a result-effective variable (Reinmuth, paragraph 8 and Wu, paragraph 46). The examiner now notes that optimization of result effective variables through routine experimentation is an obviousness expedient and not a patentable distinction. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Reinmuth further in view of Wu to explicitly include where the width of the widened regions range from at least 10-20 µm and the depth of the opening is less than 5 µm and the width is less than 2 µm. Doing so allows for improvements in the overall manufacturing process of the vertical trenches and via (Reinmuth, paragraphs 6-8 and Wu, paragraph 52).
Regarding Claim 17:
The combination of Reinmuth and Wu disclose a method of claim 6, but Reinmuth does not explicitly disclose where the vertical trenches are filled with a specific type of porous low-k dielectric.
Wu discloses an analogous method for fabricating a via in a semiconductor substrate (paragraphs 2-17) with vertical trenches (Figs. 5B-D elements 507/509) filled with a porous low-k dielectric (paragraphs 46-47), wherein the porous low-k dielectric is selected from the group consisting of porous organic materials, porous carbon-doped silicon oxide, silica gel, silicate aerogels, mesoporous silicon nitride, polysilicon and/or TEOS (tetraethyl orthosilicate), porous hydrogen silsesquioxane, mesoporous silicate glasses, phosphorus particles and aluminum oxide particles (paragraphs 46-47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Reinmuth further in view of Wu to explicitly include where the porous low-k dielectric is selected from the list above because both are directed to analogous methods for producing a via in a semiconductor device. Doing so improves the efficiency of the electrical connections in the semiconductor component (We, paragraph 52).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Beock et al. (CN1191384A), Miyano et al. (US20020182845A1), Reinmuth et al. (US8741774B2), Reinmuth et al. (US20140131888A1)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/Chloë E Benton/Examiner, Art Unit 2899
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