DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-16, 18-20, and 23-24 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US A1 – hereinafter Lee) in view of Park et al. (US 20120211772 A1 – hereinafter Park).
Regarding independent claim 1, Lee teaches:
(Original) A sensing substrate (S_SUB – Fig. 4 – [0076] – “sensor
substrate S_SUB”), comprising a sensing region (DD-DA – Fig. 3 – [0060] – “sensing area corresponding to the display area DD-DA”), wherein the sensing region (DD-DA) comprises a plurality of signal wires (SL1-1 to SL1-5 – Fig. 4 – [0059] – “signal lines SL1-1 to SL1-5”), on a plane parallel to the sensing substrate (S_SUB – [0076] – “the first signal lines SL1-1 and SL1-2, the second sensing electrodes IE2-1, IE2-2, and IE2-3, the second signal lines SL2-1, SL2-2, and SL2-3, the dummy electrodes DE1, DE2, and DE3, the antenna patterns AP1 and AP2, the antenna signal lines AL1 and AL2, and the antenna pads APDS may be disposed on a sensor substrate S_SUB”), an anti-static element and a fan-out region are provided on at least one side of the sensing region, the anti-static element is on a side of the fan-out region away from the sensing region, and at least part of the signal wires in the sensing region are electrically connected with the anti-static element through fan-out wires in the fan-out region.
Lee does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Park teaches
an anti-static element (ES1 – ES3 – Fig. 8 – [0148] – “touch antistatic lines ES1 to ES4”) and a fan-out region (Fig. 8 annotated, see below – [0112] – “fan-out lines” – this is considered a fan-out region, hereinafter ‘FOR’) are provided on at least one side of the sensing region (Fig. 8 annotated, see below – [0102] – “touch layer TSL may include a plurality of sensing regions and sensing electrodes” – hereinafter ‘TSR’), the anti-static element (ES1-ES3) is on a side of the fan-out region (FOR) away from the sensing region (TSR – Fig. 8 annotated, shows this), and at least part of the signal wires ([0148] – “The plurality of touch signal lines includes a plurality of touch driving lines TL and a plurality of touch sensing lines RL. In an embodiment, the touch signal lines may further include touch ground lines G1 to G6 and/or touch antistatic lines ES1 to ES4”) in the sensing region (TSR) are electrically connected ({[0023] – “the first dummy pattern is electrically connected to the touch signal lines”}, {[0281] – “a first dummy pattern DMP1_4 is connected directly to an adjacent touch signal line (a third touch antistatic line ES3 in the example shown in FIG. 25)”} – Fig. 25 shows this) with the anti-static element (ES1 to ES4) through fan-out wires (all wires must pass through the fan-out regio, each wire here is considered a fan-out wire) in the fan-out region (FOR).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the anti-static and fan-out structure as taught by Park into Lee.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of [0007] – “to display images in a display area that is of a relatively small size, in which the devices also have a non-display area in which images are not displayed, to reduce a difference in a visual sensation of an image in a portion of a display area where signal lines are disposed as compared to an image in a portion of the display area where no signal lines are disposed.” The anti-static lines prevent possible circuit damage from charges that could cross signal wires due to their proximity to each other.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park and Han et al. (US 20220115473 A1 – hereinafter Han).
Regarding claim 2, Lee as modified by Park, teaches claim 1 from which claim 2 depends. Lee further teaches
(Original) The sensing substrate according to claim 1, further
comprising a drive port, wherein the anti-static element comprises a first anti-static unit and the fan-out region comprises a first anti-static fan-out region;
on a plane parallel to the sensing substrate (S_SUB) , the sensing region (TSA – Fig. 4 – [0077] – “touch sensing area TSA may overlap the display area (e.g., DD-DA”) comprises a first side (Fig. 3 annotated, see below – hereinafter ‘D1’) and a second side (Fig. 3 annotated, see below – hereinafter ‘D2’) disposed opposite to each other along a first direction (DR1 – Fig. 3 – [0046] – “first direction DR1”), on the first direction (DR1), the drive port (SL-P – Fig. 3 – [0069] – “pad portion SL-P” – it is interpreted that the drive port is contained in SL-P) is on a side of the first side (D1) away from the second side (D2), the first anti-static unit (TGL – Fig. 4 shows TGL at the side of the image corresponding to D2 in Fig. 3) is on a side of the second side (D2) away from the first side (D1), and the first anti-static fan-out region is between the sensing region (DD-DA – Fig. 4 shows this) and the first anti-static unit.
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Lee does not expressly disclose the other limitations of claim 2.
However, in an analogous art, Park teaches
a drive port ([0097 – “A driver board 30 may be connected to the end of the subsidiary region SR of the display panel 10.” – this is interpreted as containing a drive port to make the connection).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the drive port structure as taught by Park into Lee.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result as stated above in claim 1.
Lee and Park do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Han teaches
the anti-static element (306 – Fig. 18 – [0135] – “antistatic region 306”) comprises a first anti-static unit (306 – the unit is the element) and the fan-out region comprises a first anti-static fan-out region (305 – Fig. 18 – [0135] – “fan-out region 305”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the anti-static and fan-out structure as taught by Han into Lee and Park.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result of [0003] – “An Organic Light Emitting Diode (abbreviated as OLED) is an active light emitting display component, and has advantages of self-light-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, etc.”
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park and He et al. (US 20210167143 A1 – hereinafter He).
Regarding claim 23, Lee as modified by Park, teaches claim 1 from which claim 23 depends. Lee and Park do not expressly disclose the limitations of claim 23.
However, in an analogous art, He teaches
(Currently amended) A sensing device (30 – Fig. 1 – [0042] – “photosensitive device 30”), comprising a detection layer (30 – Fig. 1 – [0039] – “plurality of photosensitive devices 30”) and the sensing substrate (20 – Fig. 1 – [0039] – “a thin film transistor structure layer 20” – this is a sensing substrate) according to claim 1, wherein the sensing substrate (20) comprises a base substrate (10 – Fig. 1 – [0039] – “substrate 10”) and a read layer (Fig. 1 annotated, see below – [0039] – “the display backplane includes a substrate 10; a thin film transistor structure layer 20 disposed on one side of the substrate 10 and including a plurality of thin film transistors, a gate insulating layer and an interlayer dielectric layer 26; and a plurality of photosensitive devices 30” – hereinafter ‘RL’) disposed on the base substrate (10) and the detection layer (30) is disposed on a side of the read layer (RL) away from the base substrate (10 – [0039] – “a plurality of photosensitive devices 30 spaced apart from the thin film transistor structure layer 20 and disposed on one side of the thin film transistor structure layer 20 away from the substrate”).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sensing device structure as taught by He into Lee and Park.
An ordinary artisan would have been motivated to use the known technique of He in the manner set forth above to produce the predictable result of [0003] – “the corresponding compensation is performed by a method by incorporating photosensitive devices in pixels to sense a luminous intensity of the OLED and feeding back signals detected by the photosensitive devices to the OLED.”
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park, He, and Liang et al. (US 20210013347 A1 – hereinafter Liang).
Regarding claim 24, Lee as modified by Park and He, teaches claim 23 from which claim 24 depends. Lee and Park do not expressly disclose the limitations of claim 24.
However, in an analogous art, He teaches
(Original) The sensing device according to claim 23, wherein on a plane parallel to the sensing substrate (20), the sensing substrate (20) comprises a sensing region (Fig. 1 annotated, see above – hereinafter ‘SR’) and the sensing region (SR) is provided with a plurality of first electrodes (31 – Fig. 1 – [0043] – “first electrode 31”) electrically connected with the read layer (RL – Fig. 1 shows this); in a direction perpendicular to a plane where the sensing substrate (20) is located, the plurality of first electrodes (31) are on a side of the read layer (RL) away from the base substrate (10), and the detection layer (30) comprises a photoelectric conversion layer (32 – Fig. 1 – [0043] – “photosensitive sensor 32 may be a PIN-type photodiode” – this is interpreted as a conversion layer) disposed on a side of the first electrodes (31) away from the base substrate (10 – Fig. 1 shows this) and a second electrode layer (33 – Fig. 1 – [0043] – “second electrode 33”) disposed on a side of the photoelectric conversion layer (32) away from the base substrate (10 – Fig. 1 shows this);
on a plane parallel to the sensing substrate, a bias element is provided on at least one side of the sensing region and the bias element is electrically connected with the second electrode layer and configured to provide a bias voltage to the second electrode layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sensing device structure as taught by He into Lee and Park.
An ordinary artisan would have been motivated to use the known technique of He in the manner set forth above to produce the predictable result of as stated above in claim 23.
Lee, Park, and He do not expressly disclose the other limitations of claim 24.
However, in an analogous art, Liang teaches
on a plane parallel to the sensing substrate ([0004] – “the present disclosure provides a flat panel detection substrate” – hereinafter ‘GL’), a bias element (11 – Fig. 1 – [0045] – “bias electrode 11”) is provided on at least one side of the sensing region (the detection substrate is a detection region – hereinafter ‘100’) and the bias element (11) is electrically connected with the second electrode layer (12 – Fig. 1 – [0047] – “the semiconductor layer 13 is designed to directly contact the bias electrode 11 and the sense electrode 12, and in this way, the semiconductor layer 13 has double-layer functions, i.e., a function of a photoelectric conversion layer and a function of a dielectric layer”) and configured to provide a bias voltage ([0050] – “the external bias voltage is applied to portion of the semiconductor layer 13 serving as the dielectric layer with high resistance”) to the second electrode layer (12 – the bias voltage is applied thorough the layer 13).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the bias element structure as taught by Liang into Lee, Park, and He.
An ordinary artisan would have been motivated to use the known technique of Liang in the manner set forth above to produce the predictable result of [0050] – “When the voltage is high enough, the portion of the semiconductor layer 13 serving as the dielectric layer can be electrically conducting due to the F-N tunneling effect of electrons. The signal written into the detection control line may control the on and off states of the thin film transistor 14, so as to realize the reading and the storage of the electrical signal generated in the semiconductor material, thereby achieving the purpose of detection.”
Allowable Subject Matter
Claims 3-10, 12-16, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, prior art of record fails to teach or suggest a size of a side of the first anti-static fan-out region close to the sensing region along a second direction is less than a size of a side of the first anti-static fan-out region close to the first anti-static unit along the second direction, on a plane parallel to the sensing substrate.
Claims 4-10, 12-16, and 18-20 depend on claim 3 and would be allowable is claim 3 is written in an independent form.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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