DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8, 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto et al. (US 2019/0181078 A1).
Regarding claim 1, Yamamoto teaches a semiconductor device (package 10 in Fig. 1-3 of Yamamoto) comprising:
a first chip mounting portion (chip mounting region 15 of T2);
a second chip mounting portion (chip mounting region 15 of T1);
a first semiconductor chip (T2) having a main surface (top surface of T1) and a back surface (bottom surface of T2) on a side opposite to the main surface and mounted on the first chip mounting portion (as defined above and shown in Figs. 1 & 3);
a second semiconductor chip (T1) having a main surface (bottom surface of T1) and a back surface (top surface of T1) on a side opposite to the main surface and mounted on the second chip mounting portion (as defined above and shown in Figs. 1 & 3); and
an insulator portion (molding compound 60) configured to seal at least a part of the first chip mounting portion, at least a part of the second chip mounting portion, the first semiconductor chip, and the second semiconductor chip (as shown in Fig. 1 of Yamamoto),
wherein the first semiconductor chip has a source electrode (S of T2 in Fig. 1) formed on a side of the main surface of the first semiconductor chip and a drain electrode (D of T2) formed on a side of the back surface of the first semiconductor chip, and is mounted on the first chip mounting portion such that the drain electrode faces the first chip mounting portion (as shown in Fig. 1 of Yamamoto),
wherein the second semiconductor chip has a source electrode (S of T1 in Fig. 1) formed on a side of the main surface of the second semiconductor chip and a drain electrode (D of T1 in Fig. 1) formed on a side of the back surface of the second semiconductor chip, and is mounted on the second chip mounting portion such that the source electrode faces the second chip mounting portion (as shown in Fig. 1 of Yamamoto), and
wherein a first wiring (connecting portion between the two chip mounting regions 15 of T2 and T1, as shown in Fig. 1 of Yamamoto) configured to electrically connect the source electrode of the first semiconductor chip and the drain electrode of the second semiconductor chip is formed in the insulator portion.
Regarding claim 2, Yamamoto teaches all limitations of the semiconductor device according to claim 1, and further comprising a third semiconductor chip (23 in Fig. 3 of Yamamoto) sealed with the insulator portion and having a plurality of electrodes (the electrodes on top of chip 23 in Fig. 3 to which the wires 42 are bonded to),
wherein the first semiconductor chip further has a gate electrode (G of T2) formed on the side of the main surface of the first semiconductor chip (as shown in Fig. 3 of Yamamoto),
wherein the second semiconductor chip further has a gate electrode (G of T1) formed on the side of the main surface of the second semiconductor chip (as shown in Fig. 3 of Yamamoto), and
wherein a second wiring (42 in Fig. 3 of Yamamoto) configured to electrically connect a first electrode (the electrode on top of chip 23 that is connected to wiring 42, as shown in Fig. 3 of Yamamoto) of the plurality of electrodes of the third semiconductor chip (chip 23) and the gate electrode of the first semiconductor chip (T2) is formed in the insulator portion (as shown in Fig. 3).
Regarding claim 3, Yamamoto teaches all limitations of the semiconductor device according to claim 2, and also teaches wherein the first wiring and the second wiring are formed in a same layer (these are wirings from the top of controller chip 23, as shown in Fig. 3).
Regarding claim 4, Yamamoto teaches all limitations of the semiconductor device according to claim 2, and further comprising a third chip mounting portion (portion of substrate on which the chip 23 is mounted) sealed at least partially with the insulator portion and configured to mount the third semiconductor chip (as described in [0030] of Yamamoto).
Regarding claim 5, Yamamoto teaches all limitations of the semiconductor device according to claim 2, and also teaches wherein a third wiring (41 in Fig. 3 of Yamamoto) configured to electrically connect a second electrode (the electrode on top of chip 23 that is connected to the wiring 41) of the plurality of electrodes of the third semiconductor chip and the gate electrode of the second semiconductor chip is formed in the insulator portion (as described in [0030] of Yamamoto).
Regarding claim 8, Yamamoto teaches all limitations of the semiconductor device according to claim 2, and further comprising a lead (terminals 11, 12 at the edges of the package in Figs. 1 & 3 of Yamamoto) sealed at least partially with the insulator portion, wherein a fourth wiring (wirings connecting the pads on top of chip 23 to the terminals at the edges) configured to electrically connect a third electrode of the plurality of electrodes of the third semiconductor chip and the lead is formed in the insulator portion.
Regarding claim 11, Yamamoto teaches all limitations of the semiconductor device according to claim 2, and also teaches wherein the first chip mounting portion and the second chip mounting portion are exposed on a back surface of the insulator portion (as shown in Fig. 1 of Yamamoto).
Regarding claim 12, Yamamoto teaches all limitations of the semiconductor device according to claim 2, and also teaches wherein a control circuit (50 in Fig. 2 of Yamamoto) configured to control the first semiconductor chip and the second semiconductor chip is formed in the third semiconductor chip (as described in [0028] of Yamamoto).
Regarding claim 13, Yamamoto teaches all limitations of the semiconductor device according to claim 2, and also teaches wherein a field effect transistor (FET in T2 described in [0055] of Yamamoto) for high side switch is formed in the first semiconductor chip, and wherein a field effect transistor (FET in T1 described in [0055] of Yamamoto) for low side switch is formed in the second semiconductor chip.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Yang (US 2008/0315416 A1).
Regarding claim 6, Yamamoto teaches all limitations of the semiconductor device according to claim 5, and further comprising: a gate connection conductor portion (16 in Fig. 3 of Yamamoto) sealed with the insulator portion and configured to face and electrically connected to the gate electrode of the second semiconductor chip (as shown in Fig. 3 of Yamamoto).
But Yamamoto does not teach the semiconductor device comprising: a conductive first plug portion arranged between the gate connection conductor portion and the third wiring and configured to electrically connect the gate connection conductor portion and the third wiring, wherein the gate electrode of the second semiconductor chip is electrically connected to the second electrode of the third semiconductor chip via the gate connection conductor portion, the first plug portion, and the third wiring.
Yang teaches a package structure (Fig. 1 of Yang). The package structure comprises: a semiconductor chip (100) on a substrate (120); a lower wiring (106a) routing the electrical signals from the contacts (102) on a bottom surface of the substrate to an upper wiring (106b) on top surface of the substrate, the lower and upper wirings are connected by a via (112).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the wirings and via to connected between the second semiconductor chip and the third semiconductor chip in order to have high density of interconnections.
As incorporated, the lower wiring 106a of Yang is identified as the third wiring in the claim.
Regarding claim 7, Yamamoto in view of Yang teaches all limitations of the semiconductor device according to claim 6, and also teaches wherein the first wiring and the third wiring are formed in a same layer (as combined in claim 6 above, the lower wiring 106a is the same as the connecting portion of the pads 15 in Fig. 1 of Yamamoto).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Wagner et al. (US 2023/0282615 A1).
Regarding claim 9, Yamamoto teaches all limitations of the semiconductor device according to claim 8, but does not teach the semiconductor device further comprising a conductive second plug portion arranged between the lead and the fourth wiring and configured to electrically connect the lead and the fourth wiring, wherein the lead is electrically connected to the third electrode of the third semiconductor chip via the second plug portion and the fourth wiring.
Wagner teaches a package structure (100 in Fig. 1 of Wagner). The package structure comprises: a semiconductor chip (108-4,5,6) on a substrate (102); an upper wiring routing the electrical signals from the contacts on a top surface of the substrate to a lower wiring which are connected to external contacts on top surface of the substrate (as shown in Fig. 1 of Wagner); wherein the lower and upper wirings are connected by a conductive plug (120).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the wirings and via to connected between the third semiconductor chip and the terminals as according to Wagner in order to have high density of interconnections.
As incorporated, the lower wiring is identified as fourth wiring layer in the claim.
Regarding claim 10, Yamamoto teaches all limitations of the semiconductor device according to claim 9, and also teaches wherein the first wiring and the fourth wiring are formed in a same layer (as combined in claim 9 above).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Sander (US 2007/0252265 A1).
Regarding claim 14, Yamamoto teaches all limitations of the semiconductor device according to claim 1, but does not teach the semiconductor device further comprising: a fourth semiconductor chip sealed with the insulator portion, having a main surface and a back surface on a side opposite to the main surface, and mounted on the first chip mounting portion; and a fifth semiconductor chip sealed with the insulator portion, having a main surface and a back surface on a side opposite to the main surface, and mounted on the second chip mounting portion, wherein the fourth semiconductor chip has a source electrode formed on a side of the main surface of the fourth semiconductor chip and a drain electrode formed on a side of the back surface of the fourth semiconductor chip, and is mounted on the first chip mounting portion such that the drain electrode faces the first chip mounting portion, wherein the fifth semiconductor chip has a source electrode formed on a side of the main surface of the fifth semiconductor chip and a drain electrode formed on a side of the back surface of the fifth semiconductor chip, and is mounted on the second chip mounting portion such that the source electrode faces the second chip mounting portion, and wherein a fifth wiring configured to electrically connect the source electrode of the fourth semiconductor chip and the drain electrode of the fifth semiconductor chip is formed in the insulator portion.
Sander teaches a semiconductor device (41 in Fig. 2 of Sander) that comprises: a control chip (IC) in the middle; four power semiconductor chips (P1-P2, N1-N2) positioned on two sides of the control chip; two n-channel power chips (N1-N2) are low-side switches having source electrodes on the bottom surface and drain electrodes (D1, D2) on top surface of these chips; two p-channel power chips (P1, P2) are high-side switches having source electrodes (S3-S4) on the top surface and drain electrodes on bottom surface of these chips.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have added more power semiconductor chips to the device of Yamamoto in order to have handled higher power.
Both Yamamoto’s device and Sander’s device are power with similar configurations (having high/low-side switches). The first power chips can be identified as first and second semiconductor chips of the claim 1, and the control chip as the third chip, the remaining power chips as the fourth and fifth semiconductor chips as recited in the claim.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Sander, and further in view of Hartig (US 2021/0178567 A1).
Regarding claim 15, Yamamoto in view of Sander teaches all limitations of the semiconductor device according to claim 14, but does not explicitly teaches further comprising: a sixth semiconductor chip sealed with the insulator portion, having a main surface and a back surface on a side opposite to the main surface, and mounted on the first chip mounting portion; and a seventh semiconductor chip sealed with the insulator portion, having a main surface and a back surface on a side opposite to the main surface, and mounted on the second chip mounting portion, wherein the sixth semiconductor chip has a source electrode formed on a side of the main surface of the sixth semiconductor chip and a drain electrode formed on a side of the back surface of the sixth semiconductor chip, and is mounted on the first chip mounting portion such that the drain electrode faces the first chip mounting portion, wherein the seventh semiconductor chip has a source electrode formed on a side of the main surface of the seventh semiconductor chip and a drain electrode formed on a side of the back surface of the seventh semiconductor chip, and is mounted on the second chip mounting portion such that the source electrode faces the second chip mounting portion, and wherein a sixth wiring configured to electrically connect the source electrode of the sixth semiconductor chip and the drain electrode of the seventh semiconductor chip is formed in the insulator portion.
Hartig teaches a circuit (Fig. 6 of Hartig) which is an H-bridge circuit that comprises size high-side semiconductor chips and six low-side semiconductor chips (62 in Fig. 6, see [0003] and [0026] of Hartig).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have added more power semiconductor chips to the device of Yamamoto in order to have handled higher power.
As incorporated, the first, second, fourth to thirteenth semiconductor chips are assigned to high-side and low-side semiconductor chips appropriately.
Regarding claim 16, Yamamoto-Sander-Hartig teaches all limitations of the semiconductor device according to claim 15, and also teaches the semiconductor device further comprising: an eighth semiconductor chip sealed with the insulator portion and having a plurality of electrodes; and a ninth semiconductor chip sealed with the insulator portion and having a plurality of electrodes, wherein the eighth semiconductor chip includes a first control circuit configured to control the first semiconductor chip, the fourth semiconductor chip, and the sixth semiconductor chip, and wherein the ninth semiconductor chip includes a second control circuit configured to control the second semiconductor chip, the fifth semiconductor chip, and the eighth semiconductor chip (as combined in claim 15 above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
