Prosecution Insights
Last updated: July 17, 2026
Application No. 18/705,846

IMAGING DEVICE AND ELECTRONIC APPARATUS

Non-Final OA §103
Filed
Apr 29, 2024
Priority
Nov 05, 2021 — JP 2021-181454 +1 more
Examiner
CHIU, TSZ K
Art Unit
Tech Center
Assignee
Sony Group Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
536 granted / 677 resolved
+19.2% vs TC avg
Moderate +11% lift
Without
With
+10.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
37 currently pending
Career history
711
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
69.9%
+29.9% vs TC avg
§102
21.3%
-18.7% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 677 resolved cases

Office Action

§103
DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). Status of claim(s) to be treated in this office action: Independent: 1 and 15. Pending: 1-15. Information Disclosure Statement Applicant’s IDS(s) submitted on 4/29/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record. Specification The disclosure is objected to because of the following informalities: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: IMAGING DEVICE WITH RADIALLY DISTRIBUTED LOW-SENSITIVITY PIXELS. Claim Rejections - 35 USC § 103 The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-15 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jung et al., US PG pub. 20220165765 A1. Re: Independent Claim 1, Jung discloses a semiconductor substrate (220, fig. 5) including a first surface (BS, fig. 5) and a second surface (FS, fig. 5) that are opposed to each other, and including a pixel array unit (PA, fig. 3) in which multiple unit pixels (px, fig. 4) are arranged in a matrix; multiple first pixels (PD1, fig. 4) each provided in corresponding one of the multiple unit pixels (px, fig. 4); and multiple second pixels (PD2, fig. 4) that are each provided in corresponding one of the multiple unit pixels (px, fig. 4), wherein the multiple second pixels (PD2, fig. 4) are each disposed in corresponding one of the unit pixels to allow the multiple second pixels (PD2, fig. 4) to be equal to each other in distance from a center of the pixel array unit (PA, fig. 3), on a basis of respective positions, in the pixel array unit (PA, fig. 3), of the multiple unit pixels (px, fig. 4) in which the respective second pixels (PD2, fig. 4) are provided, in a planar view. Jung discloses the power supply voltage line VDL transfers a constant power supply voltage, and the plurality of transfer signal lines TGL1, TGL2 and TGL3 placed in one row independently transfer first through third transfer signals, respectively, to transfer the charge generated by the photoelectric conversion elements PD1 and PD2 of the pixel region PX to the readout element (¶0130). Jung is silent regarding: convert a smaller amount of charge per unit time than the multiple first pixels (PD1, fig. 4). However, although these limitations have been considered by the Examiner, they pertain to the manner in which the device operates. It has been held that a claim containing a recitation pertaining to the manner of operation is not deemed to patentably distinguish the claimed device from a prior art device that is structurally identical. The device of Jung is structurally identical to the Applicant s claimed device. In addition, since the only distinction between the Applicant's claimed device and Jung's is recited in functional language, it is incumbent upon the Applicant to demonstrate that Jung's device is not capable of operating as claimed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that such functional distinctions do not confer patentability when compared with prior art devices like Jung. Re: Claim 2, Jung discloses all the limitations of claim 1 on which this claim depends. Jung further discloses: wherein the multiple second pixels (PD2, fig. 4) each disposed in corresponding one of the multiple unit pixels (px, fig. 4) are disposed point-symmetrically about the center of the pixel array unit (PA, fig. 3), in a planar view. Re: Claim 3, Jung discloses all the limitations of claim 1 on which this claim depends. Jung further discloses: wherein the pixel array unit (PA, fig. 3) has an approximately rectangular shape, and is divided into four regions (four region for example 4x4 PX region, fig. 3) in a first direction (x direction, fig. 3) and a second direction (y direction, fig. 3) that are orthogonal in a planar view, the respective four regions (four region for example 4x4 PX region, fig. 3) having approximately equal areas, and in the four regions (four region for example 4x4 PX region, fig. 3), the multiple second pixels (PD2, fig. 4) each disposed in corresponding one of the multiple unit pixels (px, fig. 4) are disposed line-symmetrically about the first direction (x direction, fig. 3) and the second direction (y direction, fig. 3). Re: Claim 4, Jung discloses all the limitations of claim 3 on which this claim depends. Jung further discloses: multiple readout circuits (150, fig. 1;¶0032) that each read out charge (¶0035) generated in corresponding one of the multiple unit pixels (px, fig. 4), wherein the multiple readout circuits (150, fig. 1;¶0032) each include multiple transistors (¶0132), and the multiple transistors (¶0132) included in each of the multiple readout circuits (150, fig. 1;¶0032) are disposed line- symmetrically about the first direction (x direction, fig. 3) and the second direction (y direction, fig. 3) in the four regions (four region for example 4x4 PX region, fig. 3). Re: Claim 5, Jung discloses all the limitations of claim 1 on which this claim depends. Jung further discloses: wherein the multiple first pixels (PD1, fig. 4) and the multiple second pixels (PD2, fig. 4) each further include corresponding one of multiple first photoelectric converters and corresponding one of multiple second photoelectric converters, respectively, the multiple first photoelectric converters and the multiple second photoelectric converters generating charge (¶0133-¶0134) according to an amount of received light by photoelectric conversion, the multiple first photoelectric converters and the multiple second photoelectric converters are each embedded and provided in the semiconductor substrate (220, fig. 5), and the multiple first photoelectric converters and the multiple second photoelectric converters are electrically isolated from each other by an element isolator (separation film 222, fig. 5) extending between the first surface (BS, fig. 5) and the second surface (FS, fig. 5) of the semiconductor substrate (220, fig. 5). Re: Claim 6, Jung discloses all the limitations of claim 5 on which this claim depends. Jung further discloses: wherein the element isolator (separation film 222, fig. 5) includes an impurity injected region (¶0063). Re: Claim 7, Jung discloses all the limitations of claim 5 on which this claim depends. Jung further discloses: wherein the element isolator (separation film 222, fig. 5) has a groove (224a/224b, 222 and 271-273 in substrate 220, fig. 5) provided in the semiconductor substrate (220, fig. 5). Re: Claim 8, Jung discloses all the limitations of claim 7 on which this claim depends. Jung further discloses: wherein the groove (224a/224b, 222 and 271-273 in substrate 220, fig. 5) extends from the first surface (BS, fig. 5) toward the second surface (FS, fig. 5) and includes a bottom portion within the semiconductor substrate (220, fig. 5). Re: Claim 9, Jung discloses all the limitations of claim 7 on which this claim depends. Jung further discloses: wherein the groove (224a/224b, 222 and 271-273 in substrate 220, fig. 5) passes through from the first surface (BS, fig. 5) to the second surface (FS, fig. 5). Re: Claim 10, Jung discloses all the limitations of claim 7 on which this claim depends. Jung further discloses: wherein an oxide film (¶0063) is embedded in the groove (224a/224b, 222 and 271-273 in substrate 220, fig. 5). Re: Claim 11, Jung discloses all the limitations of claim 7 on which this claim depends. Jung further discloses: wherein polysilicon (¶0063) is embedded in the groove (224a/224b, 222 and 271-273 in substrate 220, fig. 5). Re: Claim 12, Jung discloses all the limitations of claim 7 on which this claim depends. Jung further discloses: wherein tungsten (¶0070) is embedded in the groove (224a/224b, 222 and 271-273 in substrate 220, fig. 5). Re: Claim 13, Jung discloses all the limitations of claim 7 on which this claim depends. Jung further discloses: wherein a P-type solid-phase diffusion region (¶0056) is provided on a side wall of the groove (224a/224b, 222 and 271-273 in substrate 220, fig. 5). Re: Claim 14, Jung discloses all the limitations of claim 7 on which this claim depends. Jung further discloses: wherein an N-type solid-phase diffusion region (¶0056) is provided on a side wall of the groove (224a/224b, 222 and 271-273 in substrate 220, fig. 5). Re: Independent Claim 15, Jung discloses electronic apparatus (apparatus for example shown in figure 16) comprising an imaging device including a semiconductor substrate (220, fig. 5) including a first surface (BS, fig. 5) and a second surface (FS, fig. 5) that are opposed to each other, and including a pixel array unit (PA, fig. 3) in which multiple unit pixels (px, fig. 4) are arranged in a matrix (as shown in figure 3 pixel in matrix), multiple first pixels (PD1, fig. 4) each provided in corresponding one of the multiple unit pixels (px, fig. 4), and multiple second pixels (PD2, fig. 4) that are each provided in corresponding one of the multiple unit pixels (px, fig. 4), wherein the multiple second pixels (PD2, fig. 4) are each disposed in corresponding one of the unit pixels to allow the multiple second pixels (PD2, fig. 4) to be equal to each other in distance from a center of the pixel array unit (PA, fig. 3), on a basis of respective positions, in the pixel array unit (PA, fig. 3), of the multiple unit pixels (px, fig. 4) in which the respective second pixels (PD2, fig. 4) are provided, in a planar view. Jung discloses the power supply voltage line VDL transfers a constant power supply voltage, and the plurality of transfer signal lines TGL1, TGL2 and TGL3 placed in one row independently transfer first through third transfer signals, respectively, to transfer the charge generated by the photoelectric conversion elements PD1 and PD2 of the pixel region PX to the readout element (¶0130). Jung is silent regarding: convert a smaller amount of charge per unit time than the multiple first pixels (PD1, fig. 4). However, although these limitations have been considered by the Examiner, they pertain to the manner in which the device operates. It has been held that a claim containing a recitation pertaining to the manner of operation is not deemed to patentably distinguish the claimed device from a prior art device that is structurally identical. The device of Jung is structurally identical to the Applicant s claimed device. In addition, since the only distinction between the Applicant's claimed device and Jung's is recited in functional language, it is incumbent upon the Applicant to demonstrate that Jung's device is not capable of operating as claimed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that such functional distinctions do not confer patentability when compared with prior art devices like Jung. Prior art made of record and not relied upon are considered pertinent to current application disclosure. * (“Yanagita et al., US Patent 10741599 B2”) Discloses an Imaging devices and electronic apparatuses incorporating imaging devices or image pick-up elements are provided. An imaging device as disclosed can include a substrate, a first opto-electronic converter having a first area formed in the substrate, and a second opto-electronic converter having a second area formed in the substrate. The first area is larger than the second area. In addition, a light blocking wall can extend from a first surface of the substrate such that at least a portion of the light blocking wall is between the first opto-electronic converter and the second opto-electronic converter. * (“Zang et al., US Patent 11362121 B2”) discloses an image sensor includes a substrate having a plurality of small photodiodes and a plurality of large photodiodes surrounding the small photodiodes. The substrate further includes a plurality of deep trench isolation structures in regions of the substrate between ones of the small photodiodes and the large photodiodes. Each of large photodiodes having a full well capacity larger than each of the small photodiodes. The image sensor further includes an array of color filters disposed over the substrate, a first and second buffer layer disposed between the substrate and the array of color filters, metal grid structures disposed between the color filters and above the first buffer layer, and an attenuation layer portion above a region of the substrate between ones of the large and small photodiodes, the attenuation layer portion is between the first and second buffer layers and normal to an upper surface of the substrate. * (“Lee US PG pub. 20180063456 A1”) Discloses an image sensor according to some example embodiments includes a pixel array unit including a plurality of transmission signal lines and a plurality of output signal lines, and a plurality of pixels connected to the plurality of transmission signal lines and the plurality of output signal lines. Each of the plurality of pixels includes a plurality of photoelectric conversion elements, which are configured to detect and photoelectrically convert incident light. The plurality of pixels include at least one autofocusing pixel and at least one normal pixel. * (“Uesaka US PG pub. 20190006407 A1”) discloses a solid-state imaging apparatus and an electronic device that are configured to enhance the accuracy in the detection of polarization information. The solid-state imaging apparatus has a pixel array block on which pixels each including a photoelectric conversion device are arranged; a polarizer, including a conductive light-shielding material, that covers a photosensitive surface of the above-mentioned photoelectric conversion device of at least part of the above-mentioned pixels; a light-shielding film, including a conductive light-shielding material, that is arranged between the above-mentioned adjacent pixels on the photosensitive surface side of the above-mentioned photoelectric conversion device; and a wiring layer arranged on a side opposite to the photosensitive surface of the above-mentioned photoelectric conversion device, in which the above-mentioned polarizer is connected to a wiring of the above-mentioned wiring layer via the above-mentioned light-shielding film. * (“Kido et al., US PG pub. 20190096933 A1”) Discloses a solid-state imaging device and an electronic device that can expand a dynamic range in a pixel having a high-sensitivity pixel and a low-sensitivity pixel. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is arranged in a two-dimensional manner, in which the pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit having lower sensitivity than the first photoelectric conversion unit, and a size of the second photoelectric conversion unit in an optical axis direction in which light enters is smaller than a size of the first photoelectric conversion unit in the optical axis direction. * (“Asatsuma et al., US PG pub. 20210193727 A1”) discloses an imaging device and an electronic device enabling expansion of a dynamic range of the imaging device without deteriorating the image quality. Provided are a first photoelectric conversion unit, a second photoelectric conversion unit having a smaller electric charge amount to be converted per unit time than the first photoelectric conversion unit, a charge accumulation unit configured to accumulate an electric charge generated by the second photoelectric conversion unit, a charge voltage conversion unit, a first transfer gate unit configured to transfer an electric charge from the first photoelectric conversion unit to the charge voltage conversion unit, a second transfer gate unit configured to couple potentials of the charge voltage conversion unit and the charge accumulation unit, a third transfer gate unit configured to transfer an electric charge from the second photoelectric conversion unit to the charge accumulation unit, an overflow path formed under a gate electrode of the third transfer gate unit, and configured to transfer an electric charge overflowing from the second photoelectric conversion unit to the charge accumulation unit, and a light reducing unit configured to reduce light to enter the second photoelectric conversion unit. * (“Park et al., US PG pub. 20220130876 A1”) Discloses a pixel array including: a plurality of pixel groups, each pixel group including: a plurality of unit pixels respectively including photoelectric conversion elements disposed in a semiconductor substrate; trench structures disposed in the semiconductor substrate and extending in a vertical direction from a first surface of the semiconductor substrate to a second surface of the semiconductor substrate to electrically and optically separate the photoelectric conversion elements from each other; and a microlens disposed above or below the semiconductor substrate, the microlens covering all of the photoelectric conversion elements in the plurality of unit pixels to focus an incident light to the photoelectric conversion elements. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Apr 29, 2024
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
90%
With Interview (+10.6%)
3y 4m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 677 resolved cases by this examiner. Grant probability derived from career allowance rate.

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