DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . All the claims have been examined on the basis of the merit of the claims.
Priority
The present application is a 371 of PCT/CN2023095842 filed 05/23/2023 which claims priority benefits from PCT/CN2022134711 filed 11/28/2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDSes) submitted on 10/29/2024, 08/13/2025 and 07/15/2026 are considered and attached.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 25 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by CHO et al. (US-20200027939-A1, hereinafter as CHO).
In regard to claim 1, CHO discloses a display substrate, comprising: a base substrate (fig.5, display substrate comprising base substrate 110); a plurality of sub-pixels, arranged in an array along a first direction and a second direction that intersect each other on the base substrate (PX, fig.1), and comprising a plurality of pixel circuits, wherein each of the sub-pixels comprises a plurality of display units, each of the display units is independently driven by a corresponding pixel circuit (each sub-pixel that comprises a display unit is driven by the pixel circuit as shown in fig.2), and adjacent display units form a pixel unit group (fig.1); and a plurality of signal lines, wherein at least part of the signal line extends along the second direction (data line 171, fig.1, fig.4), display units comprised in at least one pixel unit group are connected to a same signal line (sub pixels group connected a single data line, fig.1), and in the second direction, the signal line comprises a first connection portion and a second connection portion, and in the first direction, a width of the first connection portion is less than a width of the second connection portion (fig.4, the data line 171 has two connection portions where the widths are different at contact holes/connection portions).
In regard to claim 2, CHO discloses the display substrate according to claim 1, wherein the display substrate comprises a first conductive layer and a functional layer stacked on the base substrate, the first conductive layer comprises a plurality of conductive structures arranged in the second direction, each of the conductive structures comprises a conductive portion electrically connected to the functional layer through a via structure, and conductive portions adjacent to each other in the second direction are spaced apart in the first direction (transistor layer of fig. 5 as the conductive layer and a functional layer as connected by contact holes such as 174).
In regard to claim 25, CHO discloses a display device, comprising the display substrate according to claim 1 (fig.1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHO in view of CHEN et al. (US-20160149163-A1, hereinafter as CHEN).
In regard to claim 8, CHO discloses the display substrate according to claim 2, CHO does not disclose further comprising a lens structure, configured to irradiate image light emitted from the plurality of sub-pixels to different viewpoint regions, wherein the lens structure comprises a plurality of lens portions arranged in the first direction and extending in the second direction; and the plurality of sub-pixels are arranged into a plurality of sub-pixel row groups, the plurality of sub-pixel row groups extend in the second direction and are arranged in the first direction, each of the sub-pixel row groups comprises at least two rows of sub-pixels, each of the sub-pixel row groups corresponds to one of the plurality of lens portions, and a plurality of viewpoint regions formed by respective sub-pixel row groups through corresponding lens portions are continuously arranged along the first direction.
CHEN discloses further comprising a lens structure, configured to irradiate image light emitted from the plurality of sub-pixels to different viewpoint regions, wherein the lens structure comprises a plurality of lens portions arranged in the first direction and extending in the second direction; and the plurality of sub-pixels are arranged into a plurality of sub-pixel row groups, the plurality of sub-pixel row groups extend in the second direction and are arranged in the first direction, each of the sub-pixel row groups comprises at least two rows of sub-pixels, each of the sub-pixel row groups corresponds to one of the plurality of lens portions, and a plurality of viewpoint regions formed by respective sub-pixel row groups through corresponding lens portions are continuously arranged along the first direction (fig.2, para 0022, a first exemplary embodiment of a light extraction structure may contain an array of lenses or set of lenses, the array of lenses or sets of lenses contain a high refractive index material having refractive index higher than the encapsulation layer or the substrate, each of the lens or set of lenses is applied between the active region of a light emitting device and the encapsulation layer or substrate layer of the light emitting device, each of the lens or set of lenses covers at least one pixel, a planarization layer between the array of lenses or sets of lenses and the encapsulation or substrate layer, the light extraction structure enhances the overall extraction efficiency of light generated by the active region to the viewer or the external light detector).
It would have been obvious to one of ordinary skill in the art, before the effective filing of the invention to use CHEN’s teachings to design micro lens array structure to increase light extraction efficiency in CHO’s invention.
Allowable Subject Matter
Claims 3-7, 10-18, 21 and 23 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
In regard to claim 3, CHO discloses the display substrate according to claim 2, wherein the functional layer comprises a semiconductor layer, a first metal layer, and a second conductive layer stacked on the base substrate; the conductive structure comprises a first conductive structure, a second conductive structure, a third conductive structure, a fourth conductive structure, a fifth conductive structure, a sixth conductive structure, a seventh conductive structure, an eighth conductive structure, a ninth conductive structure, a tenth conductive structure, and an eleventh conductive structure arranged sequentially in the second direction; the conductive portion comprises a first conductive portion, a second conductive portion, a third conductive portion, a fourth conductive portion, a fifth conductive portion, a sixth conductive portion, a seventh conductive portion, an eighth conductive portion, a ninth conductive portion, a tenth conductive portion, and an eleventh conductive portion; and the first conductive portion, the second conductive portion, the third conductive portion, the fourth conductive portion, the fifth conductive portion, the sixth conductive portion, the seventh conductive portion, the eighth conductive portion, the ninth conductive portion, the tenth conductive portion, and the eleventh conductive portion are respectively a part of the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure, the sixth conductive structure, the seventh conductive structure, the eighth conductive structure, the ninth conductive structure, the tenth conductive structure, and the eleventh conductive structure; the via structure comprises a first via structure, a second via structure, a third via structure, a fourth via structure, a fifth via structure, a sixth via structure, a seventh via structure, an eighth via structure, a ninth via structure, a tenth via structure, and an eleventh via structure; the first conductive portion is electrically connected to the semiconductor layer through the first via structure, the second conductive portion is electrically connected to the first metal layer through the second via structure, the third conductive portion is electrically connected to the semiconductor layer through the third via structure, the fourth conductive portion is electrically connected to the first metal layer through the fourth via structure, the fifth conductive portion is electrically connected to the second conductive layer through the fifth via structure, the sixth conductive portion is electrically connected to the first metal layer through the sixth via structure, the seventh conductive portion is electrically connected to the first metal layer through the seventh via structure, the eighth conductive portion is electrically connected to the semiconductor layer through the eighth via structure, the ninth conductive portion is electrically connected to the first metal layer through the ninth via structure, the tenth conductive portion is electrically connected to the first metal layer through the tenth via structure, and the eleventh conductive portion is electrically connected to the second conductive layer through the eleventh via structure; and any two adjacent portions among the first conductive portion, the second conductive portion, the third conductive portion, the fourth conductive portion, the fifth conductive portion, the sixth conductive portion, the seventh conductive portion, the eighth conductive portion, the ninth conductive portion, the tenth conductive portion, and the eleventh conductive portion in the second direction are spaced apart in the first direction.
Claims 4-7, 10-18, 21, 23 depend on claim 3.
9. (canceled)
19. (canceled)
20. (canceled)
22. (canceled)
24. (canceled)
Conclusion
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/DEEPROSE SUBEDI/Primary Examiner, Art Unit 2627
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