DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN 202210898307.2, filed on 28th Jul. 2023.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claim(s) 1 and 27 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cho et al. (US Patent/PGPub. No. 20230060062).
Regarding Claim 1, (Original)
Cho et al. teach
a display substrate ([0046], FIG. 1, i.e. substrate 100), comprising:
a display region ([0046], FIG. 1, i.e. display area DA), provided with sub-pixels ([0047], FIG. 1, i.e. pixel P may be arranged in the display area DA) and having a lower edge ([0049], FIG. 1, i.e. first edge E1) extending in a transverse direction ([0041], FIG. 1, i.e. x-axis) and a left edge ([0050], FIG. 1, i.e. second edge E2) extending in a longitudinal direction ([0041], FIG. 1, i.e. y-axis), wherein the transverse direction intersects with the longitudinal direction (FIG. 1, i.e. as shown by the figure(s) x-axis intersects y-axis), the display region (i.e. please see above citation(s)) comprises a left display region ([0121], FIG. 5, i.e. first sub-display area SDA1, second sub-display area SDA2, third sub-display area SDA3) and a right display region ([0121], FIG. 5, i.e. fourth sub-display area SDA4, and a fifth sub-display area SDA5) that are arranged in the transverse direction (FIG. 5, i.e. as shown by the figure(s) SDA1 to SDA5 arranged in x-direction (traverse)), and the left display region (i.e. please see above citation(s)) comprises a first edge display region ([0121], FIG. 5, i.e. second sub-display area SDA2, third sub-display area SDA3) extending along the left edge (FIG. 5, i.e. as shown by the figure(s) SDA2 and SDA3 extending along the left edge (E2)) and a first middle display region ([0121], FIG. 5, i.e. first sub-display area SDA1) located at a side of the first edge display region close to the right display region (FIG. 5, i.e. as shown by the figure(s) SDA1 located at the right side of SDA2/SDA3 (first edge display region) close to the right display region (SDA4/SDA5));
a non-display region ([0005], FIG. 1, i.e. “dead space” in which light-emitting diodes are not arranged); [0044], FIG. 1, i.e. peripheral area PA outside the display area DA), comprising a frame region surrounding ([0005], FIG. 1, i.e. “dead space”; [0045], FIG. 1, i.e. peripheral area PA may surround the display area DA) at least part of the display region (i.e. please see above citation(s));
a first power voltage lead ([0049], FIG. 1, i.e. common voltage supply line 10), configured to provide a first power voltage ([0061], FIG. 1, i.e. second power voltage ELVSS), and located in the frame region ([0048], FIG. 1, i.e. common voltage supply line 10 … may be arranged in the peripheral area PA), wherein the first power voltage lead (i.e. please see above citation(s)) comprises a lower lead ([0049], FIG. 1, i.e. first common voltage input part 11) extending along a portion of the lower edge corresponding to the first edge display region (FIG. 1 & 5, i.e. as shown by the figure(s) 11 extending along a portion of the lower edge (E1) corresponding to the first edge display region (SDA2/SDA3)), and the first power voltage lead does not extend along a portion of the lower edge corresponding to the first middle display region (FIG. 1 & 5, i.e. as shown by the figure(s) 11 does not extend along a portion of the lower edge (E1) corresponding to the first middle display region (SDA1));
a first power voltage line ([0048], FIG. 1, i.e. common voltage line VSL), comprising an edge voltage line ([0120], FIG. 5, i.e. second common voltage line VSL2) located in the first edge display region and ([0120], FIG. 5, i.e. “common voltage line electrically connected to the first common voltage input part 11 and … cross the display area DA”; FIG. 5, i.e. as shown by the figure(s) VSL2 located in the first edge display region (SDA2)) a middle voltage line ([0120], FIG. 5, i.e. first common voltage line VSL1) located in the first middle display region ([0120], FIG. 5, i.e. “common voltage line electrically connected to the third common voltage input part 13 and … cross the display area DA”; FIG. 5, i.e. as shown by the figure(s) VSL1 located in the first middle display region (SDA1)), wherein the edge voltage line is in contact with the lower lead (FIG. 5, i.e. as shown by the figure(s) the edge voltage line (VSL2) is in contact with the lower lead (11)) to be electrically connected with the lower lead ([0120], FIG. 5, i.e. common voltage line electrically connected to the first common voltage input part 11) so as to provide a first power voltage ([0120], FIG. 5, i.e. second common voltage) to sub-pixels located in the first edge display region (FIG. 5, i.e. as shown by the figure(s) edge voltage line (VSL2) provide second common voltage to pixels in the first edge display region (SDA2)), and the middle voltage line (i.e. please see above citation(s)) is spaced apart from the lower lead (FIG. 5, i.e. as shown by the figure(s) middle voltage line (VSL1) is spaced apart from the lower lead (11)).
Regarding Claim 27, (Currently Amended)
Cho et al. teach
a display device ([0044], FIG. 1, i.e. display panel 1), comprising the display substrate according to claim 1 (i.e. please see above citation(s)).
Response to Argument/Amendment
4. Applicants’ Preliminary Amendment, 04/30/2024, has been entered and made of record. Claim(s) 4-6, 11, 13, 15-16, 21, 23-24, and 26-27 is/are amended, Claim(s) 14, 17-20, 22, and 25 is/are cancelled. Thus, Claim(s) 1-13, 15-16, 21, 23-24, and 26-27 is/are pending in this application.
Allowable Subject Matter
5. Claim(s) 2-13, 15-16, 21, 23-24, and 26 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is an examiner’s statement of reasons for allowance:
Cho et al. (US Patent/PGPub. No. 20230060062) teach a display apparatus includes a substrate including a display area and a peripheral area outside the display area, a common voltage supply line arranged in the peripheral area and including a first common voltage input part, a second common voltage input part, and a third common voltage input part between the first and second voltage input parts each arranged in a first edge of the display area, a first common voltage line extending from the third common voltage input part and crossing the display area in a first direction, a first data line extending in the first direction across the display area, a first data input line arranged in the peripheral area, and a first connection line connecting the first data input line to the first data line.
YAMADA et al. (US PGPUB./Pat. No. 20240090281) teach a display device, a first power supply voltage line includes a first trunk wiring line, a plurality of branch wiring lines, and a second power supply voltage line includes a second trunk wiring line. The first trunk wiring line includes a first portion and a second portion. A line width of the first portion is smaller than a line width of the second portion. A frame region in a frame region provided with the first portion includes a first irregular frame edge having an irregular shape.
The subject matter of the claim(s) that could neither be found/suggested nor obviously combinable in the prior arts of record. The subject matter was a device/method including
“…wherein the first power voltage line comprises a longitudinal voltage line extending in the longitudinal direction and a transverse voltage line extending in the transverse direction, and the longitudinal voltage line and the transverse voltage line are arranged in different layers;
the longitudinal voltage line comprises an edge longitudinal voltage line located in the first edge display region, the transverse voltage line comprises an edge transverse voltage line that is located in the first edge display region and intersected with the edge longitudinal voltage line, and the edge longitudinal voltage line and the edge transverse voltage line constitute the edge voltage line;
the first power voltage lead further comprises a left lead extending along the left edge of the display region, the edge longitudinal voltage line is directly connected with the lower lead, and the edge transverse voltage line is directly connected with the left lead.” (Claim 2), in combination with the other elements (or steps) of the device or apparatus and method recited in the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH TANG LAM whose telephone number is (571) 270-3704. The examiner can normally be reached Monday to Friday 8:00 AM to 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin K Patel can be reached at (571) 272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VINH T LAM/Primary Examiner, Art Unit 2628
Prosecution Insights