CTNF 18/706,541 CTNF 84076 DETAILED ACTION Information Disclosure Statement The information disclosure statements (IDS) submitted on 5/1/24 and 1/22/26 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1, 2, 4, 5, and 7-14 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Zhu (US 2015/0340438) . As to claim 1 , Zhu teaches a semiconductor device (see annotated fig. 2 below) comprising: a body electrode (220) extending in a direction perpendicular to a main surface of a substrate (200,202); a channel layer (204) extending from a side surface of the body electrode (220) in a first direction parallel to the main surface via an insulating film (216); a source layer and a drain layer (“S/D”, 232) that are in contact with side surfaces of the channel layer (204) in a second direction perpendicular to the first direction and sandwich the channel layer (204); and a gate electrode (240) provided between the source layer and the drain layer (232) and covering the channel layer (204) with a gate insulating film (238) interposed therebetween ([0037] – [0039]). PNG media_image1.png 720 868 media_image1.png Greyscale As to claim 2 , Zhu further teaches the substrate (200,202) includes a semiconductor layer (200) and a substrate insulating layer (202) provided on the semiconductor layer (200, [0038]). As to claim 4 , Zhu further teaches a potential of the body electrode is controlled via a well (200-1) provided in the semiconductor layer (200, [0037]). As to claim 5 , Zhu further teaches the body electrode (220) is electrically connected to the well (200-1, fig. 2). As to claim 7 , Zhu further teaches the substrate insulating layer (202) is partially provided on the semiconductor layer (200, substrate insulating layer covers the semiconductor layer except where the body electrodes contacts the semiconductor layer, thus it is partially covering the semiconductor layer), and the gate electrode (240) is provided on the substrate insulating layer (202, fig. 2). As to claim 8 , Zhu further teaches the channel layer (204) is in contact with the gate electrode (240) via the gate insulating film (238) on three surfaces: side surfaces in the first direction (see fig. 3), and upper and lower surfaces in the direction perpendicular to the main surface (see fig. 3). As to claim 9 , Zhu further teaches plurality of the channel layers (204) are provided to be spaced apart from each other in the direction perpendicular to the main surface (“a direction”, see annotated fig. 2 above). As to claim 10 , Zhu further teaches the source layer and the drain layer are provided extending in the direction perpendicular to the main surface (see annotated fig. 2 above) and are electrically connected to side surfaces of the plurality of the channel layers ([0038]). As to claim 11 , Zhu further teaches the channel layer (204) is provided extending in the first direction on both sides of the body electrode (220, see annotated fig. 2 above). As to claim 12 , Zhu further teaches the channel layers provided on both sides of the body electrode have the same conductivity type ([0033]). As to claim 13 , Zhu further teaches the semiconductor device is provided line-symmetrically with respect to a straight line extending in the second direction through the body electrode (see fig. 2). As to claim 14 , Zhu further teaches the channel layer has a nanowire structure or a nanosheet structure ([0033]). Allowable Subject Matter Claims 3 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. In particular, the prior art fails to teach a potential of the body electrode is controlled from a side opposite to a side where the substrate is provided (cl. 3) and the body electrode is capacitively coupled to the well via the insulating film (cl. 6). Zhu teaches the body contact is directly connected to the well, so it is not capacitively coupled. Also, Zhu specifically teaches the body electrode is controlled from the substrate side ([0020]). 13-03 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any response to this Office Action should be faxed to (571) 273-8300 or mailed to: Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Hand-Delivered responses should be brought to: Customer Service Window Randolph Building 401 Dulany Street Alexandria, VA 22313 Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAREN KUSUMAKAR/ Primary Examiner, Art Unit 2897 5/31/26 Application/Control Number: 18/706,541 Page 2 Art Unit: 2897 Application/Control Number: 18/706,541 Page 3 Art Unit: 2897 Application/Control Number: 18/706,541 Page 4 Art Unit: 2897 Application/Control Number: 18/706,541 Page 5 Art Unit: 2897
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