Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, “task scheduling circuitry configured to allocate tasks to the plurality of processor cores”. Subsequently, claim 1 recites “wherein the task scheduling circuitry is configured, for a given task to be allocated, to determine, based on at least one physical circuit implementation property associated with a given processor core, whether the given task is allocated to the given processor core.”. These two recitations are internally inconsistent and render the claim indefinite. The first limitation implies that allocation is already allocated as a function of the scheduling circuitry, while the wherein clause refers to a task in the future sense of “to be allocated” and a determination of “whether the given task is going to be allocated to a processor core”, creating ambiguity as to whether the determining step should be future tense “to be allocated” or the wherein clause making the allocation past tense by remove the phrase “to be”. A person of ordinary skill in the art cannot determine with reasonable certainty the scope of the claim as written.
Claims 2-18 depend from indefinite claim 1 and are therefore indefinite for the same reasons.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 19 and 20 are rejected under 35 U.S.C. 101 as being directed to patent-ineligible subject matter.
Claim 19 and 20 recited a method / computer program comprising “obtaining at least one physical circuit implementation property associated with a given processor core; and selecting, based on the at least one physical circuit implementation property, whether the given task is allocated to the given processor core.” The act of selecting is a mental observation determination or act and thus is an abstract idea.
The additional element of the obtaining step is insignificant extra-solution activity (MPEP 2106.05(g)) that is further WURC that the Courts has recognized as data gathering (MPEP 2106.05(g and d)) does not amount to a practical application of the abstract idea or amount to significantly more. The processor cores are mere instructions to apply (MPEP 2106.05(f)) of generically linking the abstract idea to a general-purpose device and does not amount to a practical application of the abstract idea or amount to significantly more.
Claim 19 recites no step of actually allocating the task to the selected processor core or executing the task on the selected core and thus fails to tie the obtaining and selecting steps to any physical implementation or result. Claim 19 recites no additional elements beyond the two abstract steps. Applicant may amend claim 19 to recite the additional step of actually executing the task to the selected processor core, thereby turning it into a practical application.
Claim 20 recites “A computer program for controlling a computer to perform the method of claim 19.” A computer program standing alone, without being tied to any structural hardware element, machine, manufacture, or composition of matter, does not fall within any of the four statutory categories of 101 (process, machine, manufacture, or composition of matter) MPEP 2106.03. Claim 20 is rejected as it is directed to non-statutory subject matter in the form of software per se. Applicant may amend claim 20 to recite a non-transitory computer readable medium having stored theron instructions that, when executed by a processor, cause the processor to perform the method of claim 19.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4-6, 8-9, 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over BISWAS (US20140281610) in view of RAMARAJU (US20110119672)
In regards to claim 1, BISWAS teaches processing circuitry to execute tasks allocated to that processor core; (P.0022) “execution pipeline 106 decodes and performs various mathematical, logical, memory access, and flow control instructions…” and task scheduling circuitry configured to allocate tasks to the plurality of processor cores, (P.0033) “method 300 further includes scheduling (operation 370) an individual thread for execution on a specified core that is best suited to achieve the performance objective and migrating an executing thread from a first core to a better suited core when the better suited core indicates availability according to the identified performance objectives…” wherein the task scheduling circuitry is configured, for a given task to be allocated, to determine, based on at least one physical circuit implementation property associated with a given processor core, whether the given task is allocated to the given processor core. (P.0013) “the characterization data may further include, for each core, a minimum voltage for each of a defined set of available clock frequencies…” (P.0033) “an individual thread for execution on a specified core that is best suited to achieve the performance objective…”
However, BISWAS does not teach A system on chip comprising: a plurality of logically homogeneous processor cores. RAMARAJU teaches A system on chip comprising: (P.0011) “A multi-core system on chip and associated method of operation are described” a plurality of logically homogeneous processor cores, each processor core comprising (P.0004) “even with homogeneous multi-core systems where the cores are identical…” (P.0014) “each of the processor cores 210, 220, 230, 240”
It would have been obvious for a person of ordinary skill in the art before the effective filing date to implement the multicore processor of Biswas as a system on chip having a plurality of logically homogenous processor cores, as taught by Ramaraju.
In regards to claim 2, BISWAS teaches and a duration that a given performance level can be maintained on the given processor core. (P. 0010) “a maximum clock frequency, obtained when operating at a maximum specified supply voltage…”
However BISWAS does not teach wherein the at least one physical circuit implementation property is indicative of at least one of:an ability to dissipate heat away from the given processor core. RAMARAJU teaches wherein the at least one physical circuit implementation property is indicative of at least one of: an ability to dissipate heat away from the given processor core; (P.0013) “as well as other factors relating to the location of each core, its power supply grid, heat dissipation performance, etc…”
It would have been obvious for a person of ordinary skill before the effective filing date to incorporate the heat dissipation considerations of Ramaraju into the task scheduling system of Biswas.
In regards to claim 4, BISWAS teaches wherein the task scheduling circuitry is configured to determine whether the given task is allocated to the given processor core in dependence on at least one performance requirement associated with the given task. (P.0033) “method 300 further includes scheduling (operation 370) an individual thread for execution on a specified core” (P.0011) “allocating a single pending thread to the fastest core when speed is a primary objective. The PCU may, in some embodiments, also allocate a single pending thread to the lowest power core when power conservation is a primary objective.” (P.0031) “identifies (operation 345) a performance objective.” (P.0033) “an individual thread for execution on a specified core that is best suited to achieve the performance objective”
In regards to claim 5, BISWAS teaches and when the at least one performance requirement exceeds a threshold performance requirement, (P.0011) “the PCU may leverage this characterization information to implement a single-core turbo feature by allocating a single pending thread to the fastest core when speed is a primary objective. The PCU may, in some embodiments, also allocate a single pending thread to the lowest power core when power conservation is a primary objective.”
However, BISWAS does not teach the at least one physical circuit implementation property comprises a position of the given processor within the system on chip; the task scheduling circuitry is configured to allocate the given task to a processor core in an outer region of the system on chip. RAMARAJU teaches the at least one physical circuit implementation property comprises a position of the given processor within the system on chip; (P. 0013) “as well as other factors relating to the location of each core…” the task scheduling circuitry is configured to allocate the given task to a processor core in an outer region of the system on chip. (P.0013) “the cores in a multi-core processor can often have different operating frequencies or other performance measures. These differences are caused by variations in the electrical and physical characteristics of the transistors used to form the individual cores, as well as other factors relating to the location of each core…”
It would have been obvious for one of ordinary skill in the art before the effective filing date to modify the task scheduling system of Biswas to consider the physical position of the processor cores as taught by Ramaraju.
In regards to claim 6, BISWAS teaches the at least one physical circuit implementation property comprises a lower limit of voltage at which the given processor core can operate; (P.0010) “and a minimum supply voltage required to operate at a minimum specified operating frequency…”, and when the at least one performance requirement is less than a threshold performance requirement, the task scheduling circuitry is configured to allocate the given task to a processor core with a lower limit of voltage below a predetermined value. (P.0011) “The PCU may, in some embodiments, also allocate a single pending thread to the lowest power core when power conservation is a primary objective.”
In regards to claim 8, BISWAS teaches the at least one physical circuit implementation property comprises an upper limit of frequency at which the given processor core can operate; the given task is associated with a given frequency indicative of a performance requirement of the given task; and the task scheduling circuitry is configured to determine whether the given task is allocated to the given processor core in dependence on the given frequency. (P.0010) “for each processing core, a maximum clock frequency…” (P.0013) “If a clock frequency required to complete a specified task is specified, selected, or otherwise imposed on a system, the matrix may, in some embodiments, be consulted to determine which set of processing cores may complete that task…”
In regards to claim 9, BISWAS teaches the task scheduling circuitry is configured to allocate the given task to a processor core for which the upper limit of frequency is equal to or greater than the given frequency. (P.0013) “the matrix may, in some embodiments, be consulted to determine which set of processing cores may complete that task…” (P.0011) “allocating a single pending thread to the fastest core when speed is a primary objective.”
In regards to claim 14, BISWAS teaches the given task comprises a task already being executed by the given processor core; (P.0012) “so that as threads executing on the fastest cores are completed…” to determine, based on the at least one physical circuit implementation property, whether a different processor core is a better choice for the given task than the given processor core; (P.0026) “At least some embodiments of PCU 124 are further operable to select processing cores 102 for execution of specific threads and to migrate a thread and its corresponding performance objective or context information from a first core, e.g., first core 102-1, to a second core, e.g., second core 102-2, when the performance characteristics of second core 102-2 make second core 102-2 better suited to achieve a desired power-performance objective than first core 102-1.” and the task scheduling circuitry is responsive to determining that the different processor core for is a better choice for the given task to re-allocate the given task from the given processor core to the different processor core. (P.0033) “migrating an executing thread from a first core to a better suited core…”
Claims 15-17 correspond to claims 1, 2, and 4 respectively and are rejected for the same reasons as claims 1, 2, and 4. Further, in regard to claim 17 – since the reference teaches homogeneous processor cores may be identical in terms of design, operation or architecture, e.g. at minimum its architectural arrangement.
Claim 19 is rejected for the same reasons as claim 1. Claim 19 recites the corresponding limitations in method form.
Claim(s) 3, 7, 10, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over BISWAS (US20140281610) in view of RAMARAJU (US20110119672) and further in view of XU (US20150160975)
In regards to claim 3, BISWAS teaches an upper limit of frequency at which the given processor core can operate; (P.0010) “a maximum clock frequency, obtained when operating at a maximum specified supply voltage…”, a lower limit of voltage at which the given processor core can operate; (P.0010) “a minimum supply voltage required to operate at a minimum specified operating frequency…”
However BISWAS does not teach wherein the at least one physical circuit implementation property comprises at least one of: a position of the given processor core within the system on chip; a thermal heat transfer parameter associated with the given processor core. RAMARAJU teaches wherein the at least one physical circuit implementation property comprises at least one of: a position of the given processor core within the system on chip; (P. 0013) “as well as other factors relating to the location of each core…”, a thermal heat transfer parameter associated with the given processor core; (P.0013) “as well as other factors relating to the location of each core, its power supply grid, heat dissipation performance, etc…”
However BISWAS and RAMARAJU don’t teach a lower limit of voltage at which the given processor core can operate; a susceptibility of the given processor core to voltage droops. XU teaches a lower limit of voltage at which the given processor core can operate; (P.0010) “a minimum supply voltage required to operate at a minimum specified operating frequency…”, a susceptibility of the given processor core to voltage droops; (P.0036) “cores in the upper layers may have larger voltage droop than the lower layers...”
It would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate the additional physical implementation properties taught by Ramaraju and Xu into the task scheduling system of Biswas.
In regards to claim 7, XU teaches wherein the at least one physical circuit implementation property comprises a position, relative to a power distribution network of the system on chip, of the given processor core within the system on chip. (P.0036) “cores in the upper layers may have larger voltage droop than the lower layers because longer power delivery path consumes more power.”
It would have been obvious for one of ordinary skill in the art before the effective filing date to consider the position of processor cores relative to the power distribution network when performing the task scheduling of Biswas
In regards to claim 10, XU teaches the at least one physical circuit implementation property comprises a susceptibility of the given processor core to voltage droops; (P.0036) “cores in the upper layers may have larger voltage droop than the lower layers because longer power delivery path consumes more power.” and the task scheduling circuitry is configured to determine whether the given task is allocated to the given processor core in dependence on a droop characteristic associated with the given task. (P. 0011) “selecting the thread at the head of the queue and placing it in an available core of the bottommost available die…” (P.0039) “Whether a thread is voltage-violent or voltage-mild can be predicted according to the intrinsic droop intensity (IDI) of the thread. Voltage-violent threads have higher IDI, while voltage-mild threads have lower IDI.”
It would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate the droop-aware scheduling techniques of Xu into the task scheduling system of Biswas.
In regards to claim 13, XU teaches wherein when the droop characteristic of the given task is unknown, the task scheduling circuitry is configured to perform on-chip profiling of the given task to determine an estimate of the droop characteristic. (P. 0011) “selecting the thread at the head of the queue and placing it in an available core of the bottommost available die…” (P.0043) “micro-architectural events information captured by performance counter can be used to estimate IDI of a thread from applications so as to predict whether a thread is voltage-violent or voltage-mild… performance counter information and corresponding droop intensity of threads are gathered…”
It would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate the profiling technique of Xu into the task scheduling system of Biswas.
In regards to claim 20, XU teaches A computer program for controlling a computer to perform the method of claim 19. (P. 0011) “selecting the thread at the head of the queue and placing it in an available core of the bottommost available die…” (P.0046) “In one or more examples herein, the thread scheduling method described above may be implemented through software. Computer-readable codes for realizing the functions of the steps of the thread scheduling method can be stored in a computer-readable medium. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices and ROM and RAM devices. The computer-readable codes can be executed by one or more processing units.”
It would have been obvious for one of ordinary skill in the art to provide the task scheduling method of Biswas as modified by Ramaraju in the form of a computer program.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over BISWAS (US20140281610) in view of RAMARAJU (US20110119672) and further in view of XU (US20150160975) and further in view of Kyungwook “Frequency and Time Domain Analysis of Power Delivery Network for Monolithic 3D ICs”
In regards to claim 11, Kyungwook teaches the susceptibility of each processor core to voltage droops comprises an indication of whether each processor core is more susceptible to a resistive voltage droop or a reactive voltage droop; (Section 1, PARA 2) “The total voltage drop is decomposed into a resistive (IR)-drop component and an inductive (Ldi/dt)-drop component.”
Xu teaches the droop characteristic of the given task is indicative of whether the given task is more susceptible to the resistive voltage droop or the reactive voltage droop. (P. 0011) “selecting the thread at the head of the queue and placing it in an available core of the bottommost available die…” (P.0039) “Whether a thread is voltage-violent or voltage-mild can be predicted according to the intrinsic droop intensity (IDI) of the thread. Voltage-violent threads have higher IDI, while voltage-mild threads have lower IDI.”
It would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate the well-known classifications of voltage droop taught by Kyungwook into the droop aware scheduling framework of Xu as implemented in the task scheduling system of Biswas.
In regards to claim 12 Kyungwook teaches when the droop characteristic of the given task indicates that the given task is more susceptible to the resistive voltage droop (Section 1, PARA 2) “The total voltage drop is decomposed into a resistive (IR)-drop component and an inductive (Ldi/dt)-drop component.” when the droop characteristic of the given task indicates that the given task is more susceptible to the reactive voltage droop droop (Section 1, PARA 2) “The total voltage drop is decomposed into a resistive (IR)-drop component and an inductive (Ldi/dt)-drop component.”
XU teaches the task scheduling circuitry is configured to allocate the given task to a processor core which is less susceptible to the resistive voltage droop; and (P. 0011) “selecting the thread at the head of the queue and placing it in an available core of the bottommost available die…” (P.0040) “Arranging the voltage-violent threads in the lower layers (i.e., the layer close to power delivery system), otherwise it will induce serious voltage droop in the vertical chip stack.”, the task scheduling circuitry is configured to allocate the given task to a processor core which is less susceptible to the reactive voltage droop. (P. 0011) “selecting the thread at the head of the queue and placing it in an available core of the bottommost available die…” (P.0040) “Arranging the voltage-violent threads in the lower layers (i.e., the layer close to power delivery system), otherwise it will induce serious voltage droop in the vertical chip stack.” (P.0031) “The location of voltage-violent threads exerts an important impact on voltage droop, which is a dominant considering factor for thread scheduling.”
It would have been obvious for one of ordinary skill in the art before the effective filing date to apply the known resistive and reactive voltage droop classifications taught by Kyungwook when implementing the droop-aware task scheduling of Xu in the task scheduling framework of Biswas.
Conclusion
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/SELMAN MOHAMED ABDULLAHI/Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199
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