DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
2. Claim 11 is objected to because of the following informalities: line 6 states “general input/outpu lines” which should be corrected to “general input/output lines”
3. Claims 4 – 9 and 13 – 18 are objected to because of the following informalities:
Claims 4 and 13 recites: the capitalized phrase “TOP”
Claims 5 and 14 recites: the capitalized phrases “DIR”, “IN”, “OUT”
Claims 6 and 15 recites: the capitalized phrases “DIRB”, “OUTB”, “DIR”, “OUT”
Claims 7 and 16 recites: the capitalized phrase “TOP”
Claims 8 and 17 recites: the capitalized phrase “CNTADD”
Claims 9 and 18 recites: the capitalized phrases “DIRB”, “OUTB”, “DIR”, “OUT”
Applicant is entitled to be his/her own lexicographer however capitalized proper phrases need clarification on whether they are abbreviations or how they are particularly defined. Examiner also suggests making clarifications to the first instance such terms appear in the specification to allow for consistency of intended functionality.
Examiner is maintaining the previously cited objections with additional explanations seen in the response to arguments section below.
Appropriate correction/clarification is required.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1 – 4, 7, 8, 10 – 13, 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. (US Publication Number 2021/0181788, hereinafter “Mishra”) in view of Yakame et al. (US Publication Number 2012/0260004, hereinafter “Yakame”).
6. As per claim 1, Mishra teaches a processor arrangement, comprising a core processor (processor 104, figure 1), a peripheral unit operationally connected to the core processor (164, figure 1, paragraphs 27 and 28 peripheral unit which is connected to the processor via 130, figure 1); a given number of input/output unit lines (along bus 158/302, figure 1/3a through the interface 308, figure 3a, which allows for clock/data/output for the slave device operation, paragraphs 31 and 32, connected to peripherals 106/110/114/118/120, figure 1, paragraph 25), the peripheral unit comprising two down-counters of a given length (N-bit down counters, 324 1…k, figure 3b), the arrangement being configured to generate an event when a counter reaches zero value (decrements the counters do to zero, paragraph 31), the event synchronizing signaling on input/output unit lines (synchronizing into the shadow register 328, paragraphs 31 and 32) and communication of core processor with external peripherals (trigger events via element 322, figure 3b).
Mishra does not appear to explicitly disclose general input/output lines connected to a peripheral unit, the arrangement being further connectable to external peripherals, communications with the external peripherals being performed via the general input/output unit lines.
However, Yakame discloses general input/output lines connected to a peripheral unit, the arrangement being further connectable to external peripherals, communications with the external peripherals being performed via the general input/output unit lines (GPIO controller 18 in combination with 8, figure 5 to elements in figure 3).
Mishra and Yakame are analogous art because they are from the same field of endeavor device interconnectivity.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mishra and Yakame before him or her, to modify the connectivity of Mishra to include the mapping of Yakame because it would allow for a more regulated connectivity.
One of ordinary skill would be motivated to make such modification in order to enhance system connectivity for attached devices (paragraph 3) Therefore, it would have been obvious to combine Yakame with Mishra to obtain the invention as specified in the instant claims.
7. As per claim 11, Mishra teaches a method for controlling communication in a processor arrangement, the arrangement comprising a core processor (processor 104, figure 1), a peripheral unit operationally connected to the core processor (164, figure 1, paragraphs 27 and 28 peripheral unit which is connected to the processor via 130, figure 1); a given number of input/output unit lines (along bus 158/302, figure 1/3a through the interface 308, figure 3a, which allows for clock/data/output for the slave device operation, paragraphs 31 and 32), the arrangement being further connectable to external peripherals (external peripherals 106/110/114/118/120, figure 1, paragraph 25), the method comprising performing down-counting utilizing at least one counter of two down-counters of a given length (N-bit down counters, 324 1…k, figure 3b), generating an event when a counter reaches zero value (decrements the counters do to zero, paragraph 31), synchronizing signaling on input/output unit lines (synchronizing into the shadow register 328, paragraphs 31 and 32) and communication of core processor with external peripherals on the basis of the event (trigger events via element 322, figure 3b).
Mishra does not appear to explicitly disclose general input/output lines connected to a peripheral unit, the arrangement being further connectable to external peripherals, communications with the external peripherals being performed via the general input/output unit lines.
However, Yakame discloses general input/output lines connected to a peripheral unit, the arrangement being further connectable to external peripherals, communications with the external peripherals being performed via the general input/output unit lines (GPIO controller 18 in combination with 8, figure 5 to elements in figure 3).
Mishra and Yakame are analogous art because they are from the same field of endeavor device interconnectivity.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mishra and Yakame before him or her, to modify the connectivity of Mishra to include the mapping of Yakame because it would allow for a more regulated connectivity.
One of ordinary skill would be motivated to make such modification in order to enhance system connectivity for attached devices (paragraph 3) Therefore, it would have been obvious to combine Yakame with Mishra to obtain the invention as specified in the instant claims.
8. Mishra modified by the teachings of Yakame as seen in claim 1 above, as per claim 2, Mishra teaches a processor arrangement, wherein the two down-counters of a given length may be configured to act as a single counter having double the given length (reconfigured to a single N-bit counter with associated structure 510, figure 5, paragraph 35).
9. Mishra modified by the teachings of Yakame as seen in claim 1 above, as per claims 3 and 12, Mishra teaches a processor arrangement and method, the peripheral unit comprising one or more registers (328 1…k, figure 3b), the operation of registers being synchronized by the events from a counter of the two down-counters, the values of the registers being written or read by the core processor (synchronize registers with trigger element handling to the processor, paragraphs 30 – 32).
10. Mishra modified by the teachings of Yakame as seen in claim 1 above, as per claims 4 and 13, Mishra teaches a processor arrangement and method, wherein the peripheral unit comprises a TOP register, a down-counter being configured to load the value of the TOP register and start down-counting from the value in the TOP register (SDATA start point stored in register and transmitted, paragraph 31).
11. Mishra modified by the teachings of Yakame as seen in claim 1 above, as per claims 7 and 16, Mishra teaches a processor arrangement and method, wherein at least one of the two down-counters is configured to, when reaching zero value, perform one of the following: - load the value of the TOP register into the counter and start down-counting; - stop counting (stops counting at zero, paragraph 31).
12. Mishra modified by the teachings of Yakame as seen in claim 1 above, as per claims 8 and 17, Mishra teaches a processor arrangement and method, wherein the peripheral unit comprises a CNTADD alias register (N-bit set-point register 412, figure 4), and wherein at least one of the two down- counters is configured to, when reaching zero value continue down-counting, and when the CNTADD comprises a non-zero value add the value to the value of the counter and continue down-counting (paragraph 34, updating set point for counter to a non-zero value in relation to multiple trigger points).
13. Mishra modified by the teachings of Yakame as seen in claim 1 above, as per claims 10 and 19, Mishra teaches a processor arrangement and method, wherein the event is an event pulse (frequency trigger events, paragraph 30).
Allowable Subject Matter
14. Claims 5, 6 and 9 allowed.
Claims 14, 15, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as well as correcting the objections seen above regarding minor informalities.
Response to Arguments
15. Applicant's arguments filed 2/6/26 have been fully considered but they are not persuasive. Applicant argues the claim objections pertaining to informalities of Examiner perceived abbreviations.
With respect to Applicant’s remarks regarding terminology objections the Examiner respectfully disagrees. Although spelling out the function of a particular claim limitation might appear to make a claim unnecessarily long it would in fact allow for a clearer interpretation of the selected verbiage and benefit in inheriting the functionality that perhaps may be known to one of ordinary skill in the art. As a counter example, claim 6 of the instant application recites OUTB so assuming arguendo that OUTB is a well known phrase for one of ordinary skill in the art one could look at another patent filed by the Applicant (Nordic Semiconductor), Patent Number 12,159,138, figure 4, element RG 43 labeled as Out_B and equate it to the OUTB in the instant application. However, it is clear that the two OUTB’s have different functionality and one of ordinary skill in the art would need additional verbiage to render the element in the instant application clear for interpretation.
16. Applicant’s arguments with respect to rejections of claims 1 – 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
17. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yokoyama/Melton/Hoflehner/Shiraishi/Yang/Renner/Guo/Shimizu/Greiss has teachings of register handling therein.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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