DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in view of the new grounds of rejection necessitated by the amendment to the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13, 14, and 17-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Komai (U.S. Pub. No. 20190110009).
Regarding claim 13, Komai discloses:
An imaging element , comprising:
a pixel unit including a plurality of pixels (image sensor 3 has a plurality of pixel units 30, par. 56 and Fig. 4);
a first storage unit that is electrically connected to a first pixel among the plurality of pixels and stores a digital signal (storage unit 38 with K storage circuits 68, each storage circuit 68 is a circuit for storing a 1-bit digital value, such as a flip-flop, and with the K storage circuits 68, the storage unit 38 stores the K-bit digital signal (digital value) output by the A/D conversion unit 67, where the signal voltage output from the pixel unit 30x is converted into a digital value by the A/D conversion unit 67 and the A/D conversion unit 67 outputs a K-bit digital signal to the storage unit 38 via K signal lines, par. 74, 75 and Figs. 4, 6, and 7);
a second storage unit that is electrically connected to a second pixel among the plurality of pixels and stores a digital signal (in a different pixel blocks 32, storage unit 38 with K storage circuits 68, each storage circuit 68 is a circuit for storing a 1-bit digital value, such as a flip-flop, and with the K storage circuits 68, the storage unit 38 stores the K-bit digital signal (digital value) output by the A/D conversion unit 67, where the signal voltage output from the pixel unit 30x is converted into a digital value by the A/D conversion unit 67 and the A/D conversion unit 67 outputs a K-bit digital signal to the storage unit 38 via K signal lines, par. 74, 75 and Figs. 4, 6, and 7);
an output line to which at least one of the digital signal read out from the first storage unit and the digital signal read out from the second storage unit is output (output signal line 54 is composed of K×2 signal lines to transmit complementary signals having a K-bit digital value as output signals and in response to the row selection signal output from the row selection signal output unit 41 to the row selection signal line 51, the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 to the output signal lines 54, par. 76 and Figs. 4, 6, and 7);
an amplification unit that is electrically connected to the output line (relay amplifier circuits 35, where the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 (of storage units 38) to the output signal lines 54, and relay amplifier circuits 35 amplify the signals output from the storage units 38, par. 76, 121-122 and Figs. 4, 6, and 7);
a first switch unit for electrically connecting the first storage unit and the output line (selection switches 69 (shown as transistors in Fig. 6), where the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 to the output signal lines 54 when the selection switches 69 are turned on, where selection switches 69 are acting as a selection/buffer between K storage circuits 68 and output signal lines 54, par. 75, 76, 94, Figs. 4 and 6); and
a second switch unit for electrically connecting the second storage unit and the output line (in a different pixel block, selection switches 69 (shown as transistors in Fig. 6), where the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 to the output signal lines 54 when the selection switches 69 are turned on, where selection switches 69 are acting as a selection/buffer between K storage circuits 68 and output signal lines 54, par. 75, 76, 94, Figs. 4 and 6).
Regarding claim 14, Komai further discloses:
first switch unit includes a first transistor configured to connect the first storage unit and the output line (selection switches 69 (shown as transistors in Fig. 6), where the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 to the output signal lines 54 when the selection switches 69 are turned on, par. 75, 76, 94, Figs. 4 and 6); and
the second switch unit includes a second transistor configured to connect the second storage unit and the output line (in a different pixel block, selection switches 69 (shown as transistors in Fig. 6), where the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 to the output signal lines 54 when the selection switches 69 are turned on. par. 75, 76, 94, Figs. 4 and 6).
Regarding claim 17, Komai further discloses:
pixel unit is arranged on a first semiconductor substrate (one pixel unit 30 includes a first pixel unit 30x provided in the first semiconductor substrate 7, par. 56); and
the first storage unit and the second storage unit are arranged on a second semiconductor substrate that is stacked with the first semiconductor substrate (semiconductor substrate may be stacked with the first semiconductor substrate 7 and the second semiconductor substrate 8, where second pixel unit 30y is provided in the second semiconductor substrate 8, and where the second pixel unit 30y includes A/D conversion unit 67 and storage unit 38 including storage circuits 68 and selection switches 69, par. 56, 71, 74, 75, and Figs. 2 and 4).
Regarding claim 18, Komai further discloses:
first storage unit and the second storage unit are arranged in a position (position of each second pixel unit 30y, that includes storage unit 38 with K storage circuits 68, that is below a corresponding first pixel unit 30x, par. 51, 56, 74, and Figs. 2 and 4), in a stacking direction in which the first semiconductor substrate and the second semiconductor substrate are stacked, that faces the pixel unit (first semiconductor substrate 7 and the second semiconductor substrate 8 are stacked from the −Z direction side, where second pixel unit 30y is below a corresponding first pixel unit 30x, par. 51 and Fig. 2).
Regarding claim 19, Komai further discloses:
first switch unit and the second switch unit are arranged in a position, in the stacking direction, that faces the pixel unit (selection switches 69 in each second pixel unit 30y are positioned below corresponding first pixel units 30x, par. 51, 56, 71, 74, 75, and Figs. 2 and 4).
Regarding claim 20, Komai further discloses:
output line includes a positive and negative pair of output lines connected to the amplification unit (output signal line 54 is composed of K×2 signal lines to transmit complementary signals having a K-bit digital value as output signals, and the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 (of storage units 38) to the output signal lines 54, and relay amplifier circuits 35 amplify the signals output from the storage units 38, par. 76, 121-122, and Figs. 4, 6, and 7).
Regarding claim 21, Komai further discloses:
amplification unit is a differential amplification unit (signal levels of the signal line Q and the signal line /Q are latched, and a signal of H level or L level is output from the relay amplifier circuit 35 in accordance with the latched signal level, where in the bottom of relay amplifier circuit 35 the gates of two opposing transistors are connected to outputs of respective NAND gates that are downstream from Q and /Q output from storage unit 38, and where one terminal of each opposing transistor is commonly connected to ground while the other terminal of each opposing transistor is connected to a respective terminal of opposing transistors that output /OUT and OUT, par. 95 and Figs. 6 and 7).
Regarding claim 22, Komai further discloses:
the output line is connected to one of a positive and negative pair of inputs of the amplification unit (output signal lines 54 for Q is positive and connected as an input to relay amplifier circuit 35, par. 95 and Figs. 6 and 7), and another of the inputs of the amplification unit is connected to reference potential (/Q as a reference potential is connected to another input of relay amplifier circuit 35, par. 95 and Figs. 6 and 7).
Regarding claim 23, Komai further discloses:
An imaging device, comprising the imaging element according to claim 13 (image-capturing apparatus 1 includes image sensor 3, par. 48 and see rejection of claim 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komai (U.S. Pub. No. 20190110009) in view of Kanekal (U.S. Pat. No. 6473122).
Regarding claim 1, Komai discloses:
An imaging element (image sensor 3 has a plurality of pixel units 30, par. 56 and Fig. 4), comprising:
a pixel unit including a plurality of pixels (image sensor 3 with pixel blocks 32, par. 58);
a first storage unit that is electrically connected to a first pixel among the plurality of pixels and stores a digital signal (storage unit 38 with K storage circuits 68, each storage circuit 68 is a circuit for storing a 1-bit digital value, such as a flip-flop, and with the K storage circuits 68, the storage unit 38 stores the K-bit digital signal (digital value) output by the A/D conversion unit 67, where the signal voltage output from the pixel unit 30x is converted into a digital value by the A/D conversion unit 67 and the A/D conversion unit 67 outputs a K-bit digital signal to the storage unit 38 via K signal lines, par. 74, 75 and Figs. 4, 6, and 7);
a second storage unit that is electrically connected to a second pixel among the plurality of pixels and stores a digital signal (in a different pixel blocks 32, storage unit 38 with K storage circuits 68, each storage circuit 68 is a circuit for storing a 1-bit digital value, such as a flip-flop, and with the K storage circuits 68, the storage unit 38 stores the K-bit digital signal (digital value) output by the A/D conversion unit 67, where the signal voltage output from the pixel unit 30x is converted into a digital value by the A/D conversion unit 67 and the A/D conversion unit 67 outputs a K-bit digital signal to the storage unit 38 via K signal lines, par. 74, 75 and Figs. 4, 6, and 7),
an output line to which at least one of the digital signal read out from the first storage unit and the digital signal read out from the second storage unit is output (output signal line 54 is composed of K×2 signal lines to transmit complementary signals having a K-bit digital value as output signals and in response to the row selection signal output from the row selection signal output unit 41 to the row selection signal line 51, the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 to the output signal lines 54, par. 76 and Figs. 4, 6, and 7); and
an amplification unit that is electrically connected to the output line (relay amplifier circuits 35, where the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 (of storage units 38) to the output signal lines 54, and relay amplifier circuits 35 amplify the signals output from the storage units 38, par. 76, 121-122 and Figs. 4, 6, and 7);
a first selection/buffer unit including a first input terminal that is electrically connected to the first storage unit, and a first output terminal that is electrically connected to the output line (selection switches 69 (shown as transistors in Fig. 6), where the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 to the output signal lines 54 when the selection switches 69 are turned on, where selection switches 69 are acting as a selection/buffer between K storage circuits 68 and output signal lines 54, par. 75, 76, 94, Figs. 4 and 6); and
a second selection/buffer unit including a second input terminal that is electrically connected to the second storage unit, and a second output terminal that is electrically connected to the output line (in a different pixel block, selection switches 69 (shown as transistors in Fig. 6), where the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 to the output signal lines 54 when the selection switches 69 are turned on, where selection switches 69 are acting as a selection/buffer between K storage circuits 68 and output signal lines 54, par. 75, 76, 94, Figs. 4 and 6).
Komai is silent with regards to the selection switches being a buffer unit. Kanekal discloses this in 9:55-11:39 and Fig. 5 where a sensor cell 500 includes a tri-state buffer, where when a tri-state buffer is enabled (switching between enabled and disables) by the row read driver signal, its output can be in either a HIGH or LOW state depending on the output of the connected latch depending on the output of the connected latch. As can be see in 11:35-40 this is advantageous in that integrity of the latches' outputs to memory 204 can be assured (i.e., data corruption is prevented). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include selection switches being a buffer unit.
Regarding claim 2, Komai further discloses:
output line includes a positive and negative pair of output lines connected to the amplification unit (output signal line 54 is composed of K×2 signal lines to transmit complementary signals having a K-bit digital value as output signals, and the selection switches 69 output the K-bit digital signal stored by the K storage circuits 68 (of storage units 38) to the output signal lines 54, and relay amplifier circuits 35 amplify the signals output from the storage units 38, par. 76, 121-122, and Figs. 4, 6, and 7).
Regarding claim 3, Komai further discloses:
amplification unit is a differential amplification unit (signal levels of the signal line Q and the signal line /Q are latched, and a signal of H level or L level is output from the relay amplifier circuit 35 in accordance with the latched signal level, where in the bottom of relay amplifier circuit 35 the gates of two opposing transistors are connected to outputs of respective NAND gates that are downstream from Q and /Q output from storage unit 38, and where one terminal of each opposing transistor is commonly connected to ground while the other terminal of each opposing transistor is connected to a respective terminal of opposing transistors that output /OUT and OUT, par. 95 and Figs. 6 and 7).
Regarding claim 4, Komai further discloses:
the output line is connected to one of a positive and negative pair of inputs of the amplification unit (output signal lines 54 for Q is positive and connected as an input to relay amplifier circuit 35, par. 95 and Figs. 6 and 7), and another of the inputs of the amplification unit is connected to reference potential (/Q as a reference potential is connected to another input of relay amplifier circuit 35, par. 95 and Figs. 6 and 7).
Regarding claim 8, Komai further discloses:
An imaging device, comprising the imaging element according to claim 1 (image-capturing apparatus 1 includes image sensor 3, par. 48 and see rejection of claim 1).
Regarding claim 9, Komai further discloses:
a first conversion unit configured to convert a first signal read from the first pixel to a digital signal (A/D conversion unit 67 of one of a plurality of pixel blocks 32 of image sensor 3, A/D conversion unit 67 that converts signal voltage output from the first pixel unit 30x into a digital value and outputs a K-bit digital signal to the storage unit 38 via K signal lines, par. 58 and 74); and
a second conversion unit configured to convert a second signal read from the second pixel to a digital signal (A/D conversion unit 67 of another one of a plurality of pixel blocks 32 of image sensor 3, A/D conversion unit 67 that converts signal voltage output from the first pixel unit 30x into a digital value and outputs a K-bit digital signal to the storage unit 38 via K signal lines, par. 58 and 74);
wherein the first storage unit stores a first digital signal that is converted by the first conversion unit from the first signal to a digital signal (storage unit 38 with K storage circuits 68, each storage circuit 68 is a circuit for storing a 1-bit digital value, such as a flip-flop, and with the K storage circuits 68, the storage unit 38 stores the K-bit digital signal (digital value) output by the A/D conversion unit 67, where the signal voltage output from the pixel unit 30x is converted into a digital value by the A/D conversion unit 67 and the A/D conversion unit 67 outputs a K-bit digital signal to the storage unit 38 via K signal lines, par. 74, 75 and Figs. 4, 6, and 7); and
the second storage unit stores a second digital signal that is converted by the second conversion unit from the second signal to a digital signal (in a different pixel blocks 32, storage unit 38 with K storage circuits 68, each storage circuit 68 is a circuit for storing a 1-bit digital value, such as a flip-flop, and with the K storage circuits 68, the storage unit 38 stores the K-bit digital signal (digital value) output by the A/D conversion unit 67, where the signal voltage output from the pixel unit 30x is converted into a digital value by the A/D conversion unit 67 and the A/D conversion unit 67 outputs a K-bit digital signal to the storage unit 38 via K signal lines, par. 74, 75 and Figs. 4, 6, and 7).
Regarding claim 10, Komai further discloses:
pixel unit is arranged on a first semiconductor substrate (one pixel unit 30 includes a first pixel unit 30x provided in the first semiconductor substrate 7, par. 56); and
the first storage unit and the second storage unit are arranged on a second semiconductor substrate that is stacked with the first semiconductor substrate (semiconductor substrate may be stacked with the first semiconductor substrate 7 and the second semiconductor substrate 8, where second pixel unit 30y is provided in the second semiconductor substrate 8, and where the second pixel unit 30y includes A/D conversion unit 67 and storage unit 38 including storage circuits 68 and selection switches 69, par. 56, 71, 74, 75, and Figs. 2 and 4).
Regarding claim 11, Komai further discloses:
first storage unit and the second storage unit are arranged in a position (position of each second pixel unit 30y, that includes storage unit 38 with K storage circuits 68, that is below a corresponding first pixel unit 30x, par. 51, 56, 74, and Figs. 2 and 4), in a stacking direction in which the first semiconductor substrate and the second semiconductor substrate are stacked, that faces the pixel unit (first semiconductor substrate 7 and the second semiconductor substrate 8 are stacked from the −Z direction side, where second pixel unit 30y is below a corresponding first pixel unit 30x, par. 51 and Fig. 2).
Regarding claim 12, Komai further discloses:
first selection/buffer unit and the second selection/buffer unit are arranged in a position, in the stacking direction, that faces the pixel unit (selection switches 69 in each second pixel unit 30y are positioned below corresponding first pixel units 30x, par. 51, 56, 71, 74, 75, and Figs. 2 and 4).
Note that the selection switches 69 being buffers was shown in the rejection of claim 1.
Allowable Subject Matter
Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 15, no prior art could be located that teaches or fairly suggests the first switch unit includes a third transistor having a gate that is electrically connected to the first storage unit; the second switch unit includes a fourth transistor having a gate that is electrically connected to the second storage unit; the first transistor is arranged between the output line and the third transistor; and the second transistor is arranged between the output line and the fourth transistor, in combination with the rest of the limitations of the claim and parent claims.
Claim 16 depends on claim 15 and therefore is objected to.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS G GILES whose telephone number is (571)272-2824. The examiner can normally be reached M-F 6:45AM-3:15PM EST (HOTELING).
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639
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