DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Final communication in response to communication filed 10/16/25.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 4 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
With respect to claim 3, the recitation “an NMOS transistor provided between the low potential supply terminal and the first node, the NMOS transistor having a gate to which the signal output from the selector is input, and the second standby voltage set circuit includes a PMOS transistor provided between the high potential supply terminal and the second node, the PMOS transistor having a gate to which the signal output from the selector is input” is indefinite because it’s unclear if the NMOS and PMOS transistors are the same as or in addition to the first and second switches of claim 1, to read on figures 5 and 11?
With respect to claim 4, the recitations “a first NMOS transistor” and “a first PMOS transistor” are indefinite because it’s unclear if they’re the same as or in addition to the first and second switches of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. [20070147564] in view of D’Souza et al. [5546022].
With respect to claim 2, figures 5-7 of Fan et al. disclose a phase interpolation circuit, comprising: a scalable INV-type phase interpolation circuit [fig. 5] configured to include a current control unit including a plurality of slice circuits [505,510], the plurality of slice circuits outputting, from an output terminal [PHOUT/N1], a current signal corresponding to any signal selected from a plurality of input signals [PHINO/1] having phases different from each other, and output a signal a phase of which is interpolated on a basis of the plurality of input signals, wherein each of the slice circuits includes:
a selector [505] configured to select and output any signal of the plurality of input signals on a basis of a selection signal [PMSEL<7:0>];
a PMOS transistor [T2] having a gate to which the signal output from the selector is input, a drain connected to the output terminal, and a source;
an NMOS transistor [T3] having a gate to which the signal output from the selector is input, a drain connected to the output terminal, and a source;
a first current source [T1] provided between the source of the PMOS transistor and a high potential supply terminal [terminal at VCC];
a second current source [T4] provided between the source of the NMOS transistor and a low potential supply terminal [terminal at GND];
Fan et al does not disclose:
a first standby voltage set circuit configured to set a first node between the source of the PMOS transistor and the first current source to a standby voltage by charging and discharging a parasitic capacitance at the first node, wherein the first standby voltage set circuit has a first switch that receives the signal output from the selector to connect a first potential to the first node; and
a second standby voltage set circuit configured to set a second node between the source of the NMOS transistor and the second current source to a standby voltage by charging and discharging a parasitic capacitance at the second node, wherein the second standby voltage set circuit has a second switch that receives the signal output from the selector to connect a second potential to the second node.
However, figure 1of D’Souza discloses:
a first standby voltage set circuit [116] configured to set a first node [ 113] between the source of the PMOS transistor and the first current source to a standby voltage by charging and discharging a parasitic capacitance at the first node, wherein the first standby voltage set circuit has a first switch [116] that receives the signal output from the selector to connect a first potential [potential of VSS] to the first node; and
a second standby voltage set circuit [126] configured to set a second node [123] between the source of the NMOS transistor and the second current source to a standby voltage by charging and discharging a parasitic capacitance at the second node, wherein the second standby voltage set circuit has a second switch [126] that receives the signal output from the selector to connect a second potential [potential of VDD] to the second node.
It would have been obvious to one skilled in the art at the time the invention was made to apply first and second standby voltage circuits as seen in figure 1 of D’Souza to clamp the voltage of the connection nodes in standby since it is a known technique in the art.
Claims 1, 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. [20070147564] in view of D’Souza et al. [5546022] further in view of Vlasenko et al [10199933].
With respect to claim 1, the above combination discloses a phase interpolation circuit, comprising:
a scalable INV-type phase interpolation circuit [fig. 5] configured to include a current control unit including a plurality of slice circuits [505/510], the plurality of slice circuits outputting, from an output terminal [PHOUT], a current signal corresponding to any signal selected from a plurality of input signals [PHINO/PHIN1] having phases different from each other, and output a signal a phase of which is interpolated on a basis of the plurality of input signals,
wherein each of the slice circuits includes:
a selector [505] configured to select and output any signal of the plurality of input signals on a basis of a selection signal [PHSEL];
a first standby voltage set circuit configured to set a first node between the drain of the PMOS transistor and the first current source to a standby voltage by charging and discharging a parasitic capacitance at the first node; and
a second standby voltage set circuit configured to set a second node between the drain of the NMOS transistor and the second current source to a standby voltage by charging and discharging a parasitic capacitance at the second node.
This above combination does not disclose a PMOS transistor having a gate to which the signal output from the selector is input, a source connected to a high potential supply terminal, and a drain;
an NMOS transistor having a gate to which the signal output from the selector is input, a source connected to a low potential supply terminal, and a drain;
a first current source provided between the drain of the PMOS transistor and the output terminal;
a second current source provided between the drain of the NMOS transistor and the output terminal;
However, figure 1 of Vlasenko discloses the bias current source transistors [128, 124] connected to the output node and the input signal receiving transistors (PMOS 104 NMOS 108) connected to the power supplies and a filter on the output.
It would have been obvious to one skilled in the art at the time the invention was made to reorder the stacked transistors in the inverting circuit since the operation in both cases requires both stacked PMOS or both stacked NMOS to be ON, to change the output and a filter to eliminate noise.
With respect to claim 3 the above combination discloses the phase interpolation circuit according to claim 1, wherein the first standby voltage set circuit includes an NMOS transistor [116] provided between the low potential supply terminal [VSS terminal] and the first node, the NMOS transistor having a gate to which the signal output from the selector is input, and the second standby voltage set circuit includes a PMOS transistor [126] provided between the high potential supply terminal [VDD terminal] and the second node, the PMOS transistor having a gate to which the signal output from the selector is input.
With respect to claim 10 the above combination discloses the phase interpolation circuit according to claim 1, further comprising:
a filter [102 Vlasenko et al.] configured to include a capacitance unit charged and discharged according to a sum of current signals output from the plurality of slice circuits of the current control unit and to output a voltage signal according to an accumulated charge amount in the capacitance unit; and a waveform shaping unit [515 Fan et al] configured to shape a waveform of the voltage signal output from the filter and output the waveform-shaped signal.
Allowable Subject Matter
Claims 5-9 are allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached on 571-272-7016. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAGER/
Primary Examiner, Art Unit 2842
11/13/25