Prosecution Insights
Last updated: April 19, 2026
Application No. 18/707,974

POWER CONVERSION CIRCUIT AND METHOD

Non-Final OA §102§103
Filed
May 07, 2024
Examiner
ROSARIO BENITEZ, GUSTAVO A
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sg Micro Corp.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
597 granted / 733 resolved
+13.4% vs TC avg
Strong +25% interview lift
Without
With
+25.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
772
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
49.3%
+9.3% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 733 resolved cases

Office Action

§102 §103
DETAILED ACTION This office action is in response to the application filed on 05/07/2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/07/2024 and 09/12/2025 has been considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Interpretation In re to claims 13-19 and 21, method claims 13-19 and 21 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. Claim Objections Claims 4 and 14-17 objected to because of the following informalities: Claims 4 and 16 lines 7 and 9 “a case” should be “the case”. Claim 14 lines 1-3 “a charge path”, “a transfer path” and “a direction” this should be “the charge path”, “the transfer path” and “the direction”. Claim 15 line 2 “a discharge path” should be “the discharge path”. Claim 17 line 2 “a charging voltage level” should be “the charging voltage level”. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 6-7 and 13-18 and is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Malinin US 2016/0141975. Regarding Claims 1 and 13, Malinin teaches (Figures 3-5) A power conversion circuit (Fig. 4) used for converting an AC input voltage to a DC output voltage (AC to Out), comprising: a flying capacitor (C1); an energy storage capacitor (C2); and a rectifier (S1,D1-D2 and 400) configured to turn on a charge path through which the flying capacitor is charged by the AC input voltage (e.g. during off time of D1) or a transfer path from the flying capacitor to the energy storage capacitor (when D1 is on) selectively according to a direction of the AC input voltage (500, see fig. 5), so as to provide the DC output voltage across ends of the energy storage capacitor ( 508, see fig. 5), wherein the rectifier is further configured to stabilize the DC output voltage within a set range (with 400) by controlling a discharge path of the flying capacitor to ground (with the control of the S1 switch and 400). (For Example: Par. 46-53) Regarding Claims 2 and 14, Malinin teaches (Figures 3-5) wherein in a case that the AC input voltage is a negative voltage (fig. 5, 514), the rectifier couples the flying capacitor between two ends of an AC power supply and charges the flying capacitor by the AC power supply (504 increasing), in a case that the AC input voltage is a positive voltage (Fig. 5, 512), the rectifier couples the flying capacitor and the energy storage capacitor in series between two ends of the AC power supply (with 506 increasing) and charges the energy storage capacitor by the flying capacitor (D1 in on state). (For Example: Par. 46-53) Regarding Claims 3 and 15, Malinin teaches (Figures 3-5) wherein the rectifier is configured to control the discharge path (S1 conducting) of the flying capacitor to ground according to a charging voltage level of the energy storage capacitor (with 400). (For Example: Par. 46-53) Regarding Claims 4 and 16, Malinin teaches (Figures 3-5)wherein the rectifier comprises: a rectifying element (D1) connected between the flying capacitor (C1) and the energy storage capacitor (C2); and a switching element (S1) connected between the flying capacitor and a second end of said AC power supply (Fig. 4), wherein in a case that the AC input voltage is the positive voltage (512) and the switching element is in an off state (502), the flying capacitor transfers energy to the energy storage capacitor (with 506), in a case that the AC input voltage is the positive voltage (512) and the switching element is in an on state (502), the flying capacitor discharges to ground through the switching element (Fig. 4, s1 on state). (For Example: Par. 46-53) Regarding Claims 6 and 17, Malinin teaches (Figures 3-5)wherein the rectifier further comprises: a comparator (402), configured to control the switching element (s1) to be on and off according to a voltage on the energy storage capacitor (410). (For Example: Par. 46-53) Regarding Claims 7 and 18, Malinin teaches (Figures 3-5) wherein the comparator is a hysteresis comparator (402, Fig. 2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Malinin in view of Benabdelaziz US 20060034109. Regarding Claims 8 and 19, Malinin teaches (Figures 3-5) the circuit. Malinin does not teach wherein the switching element comprises a field effect transistor, and the rectifying element comprises a diode or a field effect transistor. Benabdelaziz teaches (Figure 4) wherein the switching element (M) comprises a field effect transistor, and the rectifying element comprises a diode or a field effect transistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Malinin to include wherein the switching element comprises a field effect transistor, and the rectifying element comprises a diode or a field effect transistor, as taught by Benabdelaziz to reduce switching losses. Claim(s) 10-12 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Malinin in view of Dai US 2019/0252995. Regarding Claims 10-12 and 21-23, Malinin teaches (Figures 3-5) the circuit. Malinin does not teach further comprising a voltage monitoring circuit, wherein the voltage monitoring circuit is configured to maintain the DC output voltage within a predetermined range, and wherein the voltage monitoring circuit comprises: one or a combination of some of an overvoltage protection circuit, an under-voltage protection circuit, a voltage regulator and a DC-DC converter; and wherein the DC-DC converter comprises a topology selected form a group consisting of Buck-type, Boost-type, Buck-Boost-type, non-inverting Buck-Boost-type, forward-type, flyback-type topologies. Benabdelaziz teaches (Figure 4) further comprising a voltage monitoring circuit(202), wherein the voltage monitoring circuit is configured to maintain the DC output voltage within a predetermined range (higher than Vmin Fig. 5, par. 74), and wherein the voltage monitoring circuit comprises: one or a combination of some of an overvoltage protection circuit, an under-voltage protection circuit, a voltage regulator and a DC-DC converter (202); and wherein the DC-DC converter comprises a topology selected form a group consisting of Buck-type, Boost-type, Buck-Boost-type (202), non-inverting Buck-Boost-type, forward-type, flyback-type topologies. (For Example: Par. 70-80) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Malinin to include further comprising a voltage monitoring circuit, wherein the voltage monitoring circuit is configured to maintain the DC output voltage within a predetermined range, and wherein the voltage monitoring circuit comprises: one or a combination of some of an overvoltage protection circuit, an under-voltage protection circuit, a voltage regulator and a DC-DC converter; and wherein the DC-DC converter comprises a topology selected form a group consisting of Buck-type, Boost-type, Buck-Boost-type, non-inverting Buck-Boost-type, forward-type, flyback-type topologies, as taught by Benabdelaziz to provide the desired level of output signal. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

May 07, 2024
Application Filed
Dec 23, 2025
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+25.3%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 733 resolved cases by this examiner. Grant probability derived from career allow rate.

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