DETAILED ACTION
This action is responsive to the following: The request for continued examination, amendments to claims filed on July 17, 2026 and the arguments made in amendment filed on July 7, 2026.
Claims 1-13, 15-16, and 19 are pending. Claims 1, 5, 9, and 15 are independent. Claims 14, and 17-18 are cancelled by applicant.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 17, 2026 has been entered.
Claims 1-13, 15-16, and 19 remain pending. Claims 14, and 17-18 are cancelled by applicant.
Claim Interpretation
The use of the terms “repeater,” ”input/output node,” ”shunt connection,” “intermediate node,” and “balance point” in claims 1-15 are being interpreted as follows:
“Repeater” is interpreted to be a 6T SRAM cell with NMOS pass gates or an 8T SRAM cell with transmission gate pass gates consisting of a NMOS and a PMOS in parallel. There is not structural difference between what is referred to as a “repeater” or “SRAM repeater” in the claims from a SRAM cell. The only difference in the claims is in the method of how it’s used but not in its structure.
“Input/output node” in refers to places on each bit line on either side of the repeater circuit. A node is commonly defined as a point where two wire or electronic components connect. The specification specifically states that benefit of the circuit in paragraph 44 is that “No signal path breaks may be included in memory column 702 using DCC repeat circuit 750.” Thus, within the context of this device there doesn’t appear to be a node but just a continuation of the bit line. Applicant clarified that the commonly held interpretation of where “an electrical connection point between the elements in a circuit” in the first sentence of paragraph 3 on page 13 of the remarks made in amendment filed on July 7, 2026. And further stated that every node is a distinct electrical connection. Thus, all elements containing “node” along the bit line are understood not to merely points along a contiguous metal line, but rather discrete points of electrical connection between wires, metal lines, or similar low impedance structures that connect to each other at the various nodes.
“Shunt Connection” is interpreted to be where the pass gate within the repeater circuit connect to the bit line. A shunt connection is normally understood to be defined as a “a device that is designed to provide a low-resistance path for an electrical current in a circuit.” And there does not appear to be any structural part of the circuit that would match that description so from context it assumed to be the connection to the bit line. Based on applicant’s remarks in the second paragraph on page 13 filed July 7, 2026, this interpretation is correct.
“Intermediate node” is interpreted to be an intermediate location on the bit line between structures. A node is commonly defined as a point where two wire or electronic components connect. The interpretation then follows that there seems to be no secondary electronic component or wire connecting to the bit line but rather just a location along bit line. Applicant clarified that the commonly held interpretation of where “an electrical connection point between the elements in a circuit” in the first sentence of paragraph 3 on page 13 of the remarks made in amendment filed on July 7, 2026. And further stated that every node is a distinct electrical connection. Thus, all elements containing “node” along the bit line are understood not to merely points along a contiguous metal line, but rather discrete points of electrical connection between wires, metal lines, or similar low impedance structures that connect to each other at the various nodes.
“Balance point” is interpreted to mean the same thing as intermediate and is just a location along the bit line.
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Claim Rejections - 35 USC § 112 - product and process
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Independent Claims 1, 5 and 15 are rejected under 35 U.S. C. 112(b) for reciting product and process in the same claim.
Applicants Claims are all directed to apparatuses and thus are structural claims. However, applicant amended the claims 1, 5 and 15 to include the following limitations:
wherein the plurality of repeaters are disposed along the pair of bit lines between groups of the plurality of memory cells, wherein each of the plurality of repeaters is separate from, and not one of, the plurality of memory cells configured to store data
wherein, during the write mode, the first switch and the second switch couple the pair of bit lines to the set of cross-coupled inverters so that the set of cross-coupled inverters receives, regenerates, and outputs the differential signal,
wherein, during the read mode, the first switch and the second switch isolate the set of cross-coupled inverters from the pair of bit lines such that a read signal on the pair of bit lines propagates from the input nodes to the output nodes along the uninterrupted bit-line signal paths without being conducted by any of the components of the respective shunt connection, including the set of cross-coupled inverters, the first switch, and the second switch,
Hereafter referred to as the first set of limitations, second set of limitations, and third set of limitations respectively.
The first set of limitations states that repeater circuits despite being connected to the same bit lines as memory cells are different. But the only difference offered by applicant is how they are configured to operate, specifically that “the plurality of memory cells configured to store data”. Applicant offers no structural difference between the repeater cell “comprising a set of cross-coupled inverters” and SRAM memory cell, which typically are comprised by a set of cross-coupled inverters, beyond how the repeater cell is used. A memory cell can be configured not to store data. In fact, it is common place in the art to place dummy cells, configured to not operate in any way at all, within memory arrays to provide buffer regions to reduce coupling effects of nearby circuitry. Thus, the way a cell is configured to be used does not represent a structural difference in an apparatus, but rather a method of operation.
The second and third set of limitations states are method of operating the repeater during a write operation and read operation respectively. Neither of these limitations contribute to a description of the apparatus claimed by applicant but merely describe the method of operating it during various operations.
MPEP 2173.05(p) states “A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b).” Therefore Claims 1, 5 and 15 are rejected for being indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 11-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bartling et al (US 20140210535 A1).
Regarding Independent Claim 1, Bartling teaches a memory array (Fig. 1: 110), comprising:
a plurality of memory cells (Fig. 4: 400) configured to store data;
a pair of bit line drivers (Fig. 11A: 1156, 1157) configured to provide a differential signal for writing data to at least some of the plurality of memory cells along a pair of bit lines (Fig. 11A: BL, BLB);
a sense amplifier (Fig. 8: 810) communicatively coupled to the bit line drivers to read data stored by at least some of the plurality of memory cells; and
a plurality of repeaters (Fig. 4: 400) connected in series to the plurality of memory cells, each repeater of the plurality of repeaters being connected, via a respective shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line), to the pair of BL drivers, wherein each repeater (Fig. 4: 400) of the plurality of repeaters comprises:
an input node (Fig. 4: BL, BLB) and an output node (Fig. 4: BL, BLB) along each bit line;
a set of cross-coupled inverters (Fig. 4: 410) configured to receive, regenerate, and output the differential signal;
a first switch (Fig. 4: 402) and a second switch (Fig. 4: 403) configured to provide the differential signal to the set of cross-coupled inverters when in write mode or bypass the set of cross-coupled inverters when in read mode (since this is a structural claim and applicant fails to outline what structures are unique to configure an SRAM cell this way its presumed that any standard SRAM cell could be configured that way.), and wherein:
the pair of bit lines (Fig. 4: BL, BLB) connect to the pair of BL drivers at a first node,
an intermediate node (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes) is placed along each bit line (Fig. 4: BL, BLB) between the first node and the input node of a first repeater of the plurality of repeaters, and
an additional intermediate node (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes) is placed along each bit line between the output node of a given repeater and the input node of a subsequent repeater.
Based on the interpretation of the claims its assumed that a repeater is merely a SRAM cell configured to operate a certain way. There is a lack of structural language to differentiate it beyond the way its configured.
Regarding Claim 2, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein the intermediate node (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes) and each additional intermediate node are placed at a balance point node (Fig. 4: BL, BLB; the balance point is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have balance points) of a respective bit line.
Regarding Claim 3, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein each repeater of the plurality of repeaters is:
a duty-cycle corrector (DCC) repeater comprising eight (8) transistors (Fig. 4: 410, 402, 403); or
an SRAM repeater comprising six (6) transistors (Fig. 4. 410, 403, 402).
Regarding Claim 4, Bartling teaches the limitations of Claim 3. Bartling further teaches the DCC repeater (Fig. 4: 400) includes the set of cross-coupled inverters (Fig. 4: 410) and a pair of transmission gates (Fig. 4: 402, 403) each including a PMOS transistor and an NMOS transistor; and
the SRAM repeater (Fig. 4: 400) includes the set of cross-coupled inverters (Fig. 4: 410) and a pair of transmission gates including an NMOS transistor (Fig. 4: 402, 403).
Regarding Independent Claim 5, Bartling teaches a repeater for a memory array, comprising:
a first input node coupled to a first bit line and a second input node coupled to a second bit line (Fig. 4: BL, BLB);
a first output node coupled to the first bit line and a second output node coupled to the second bit line (Fig. 4: BL, BLB);
a pair of switches configured to couple to the first bit line and the second bit line responsive to receiving an input signal (Fig 4: 402, 403); and
a set of cross-coupled invertors (Fig. 4: 410) coupled to the pair of switches, wherein the pair of switches (Fig 4: 402, 403) and the set of cross-coupled invertors (Fig. 4: 410) form a shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line) between the first bit line and the second bit line (Fig. 4: BL, BLB) responsive to the input signal (Fig. 4, PASS) being received by the pair of switches.
Based on the interpretation of the claims its assumed that a repeater is merely a SRAM cell configured to operate a certain way. There is a lack of structural language to differentiate it beyond the way its configured.
Regarding Claim 6, Bartling teaches the limitations of Claim 5. Bartling further teaches wherein the first input node and the second input node are coupled to a first intermediate node and a second intermediate node (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes), respectively, which are coupled to a first initial node and a second initial node, respectively, which are respectively coupled to a first bit line driver and a second bit line driver.
It is assumed that since the nodes as describe merely represent locations on a bit line as interpreted. That all the nodes are coupled to one another by virtue of all being part of the bit line.
Regarding Claim 7, Bartling teaches the limitations of Claim 6. Bartling further teaches wherein the first bit line driver (Fig. 11A: 1156) and the second bit line driver (Fig. 11A: 1157) are configured to output the input signal, the input signal being provided, via the first bit line (Fig. 11A: BL) and the second bit line (Fig. 11A: BL), respectively, to the first initial node and the second initial node, and the input signal (Fig. 11A: XOR_IN) also being provided to the pair of switches to cause the pair of switches couple to the first bit line and the second bit line, respectively.
It is assumed that since the nodes as describe merely represent locations on a bit line as interpreted. That all the nodes are coupled to one another by virtue of all being part of the bit line.
Regarding Claim 8, Bartling teaches the limitations of Claim 7. Bartling further teaches wherein the first intermediate node and the second intermediate node are placed at a first location along a portion of the first bit line and the second bit line between the first initial node and the first input node, wherein the first location is a balance point. (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes)
Independent Claim 9, Claim 9 is rejected for the same reasons as claim 1.
Regarding Claim 10, claim 10 is solely concerned with the way in which signal propagates within the bit line. It recites no additional structural limitations and no additional methods of operating. Further no structural aspects of the bit line are claimed to lead one to think that a signal wouldn’t propagate in this manner when there are bit line drivers and a repeater (SRAM cell) present. MPEP 2112(III) states “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. "There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102." In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic. Therefore, a 35 U.S.C. 102 and 103 rejection is appropriate for these types of claims as well as for composition claims.” Since Bartling anticipates the structure disclosed by applicant in claim 9, there is no reason to think that the same electrical signal would not inherently propagate within the bit lines disclosed the same way.
Regarding Claim 11, Bartling teaches the limitations of Claim 5. Bartling further teaches each switch of the pair of switches (Fig. 4: 402, 403) comprise a PMOS transistor and an NMOS transistor;
the repeater includes eight transistors (Fig. 4: 410, 402, 403); and
the repeater is a Duty-Cycle Corrector (DCC) repeater (Fig. 4: 400).
Regarding Claim 12, Bartling teaches the limitations of Claim 5. Bartling further teaches each switch of the pair of switches comprise an NMOS transistor (Fig. 4: 402, 403);
the repeater includes six transistors (Fig. 4; 402, 403, 410); and
the repeater is an SRAM repeater (Fig. 4: 402, 403, 410).
Regarding Claim 13, Bartling teaches the limitations of Claim 5. Bartling further teaches the first output node and the second output node are coupled to a memory cell (Fig: 1040), and the memory cell is coupled to an additional instance of the repeater. (Fig. 4: BL, BLB; all the nodes are interpreted as merely representing locations along the bit lines)
Regarding Claim 14, Bartling teaches the limitations of Claim 5. Bartling further teaches means (Fig. 1: 106) for reading data stored in a memory cell; and
means for writing data to a memory cell (Fig. 6: WRITE-0).
Regarding Independent Claim 15, Bartling teaches a cascading stack for a memory array (Fig. 10: 1040), comprising:
a plurality of memory cells (Fig. 4: 400); and
a plurality of repeaters (Fig. 4: 400), each coupled to a respective one of the plurality of memory cells (Fig. 10: 1041, 1040), wherein each repeater comprises (Fig. 4: 400):
a first input node (Fig. 4: BL) coupled to a first bit line and a second input node coupled to a second bit line (Fig. 4: BLB); (Input and output nodes are interpreted to just be points on the bit line on either side of a repeater and therefore are inherent to any sram cell with bit lines.)
a first output node (Fig. 4: BL) coupled to the first bit line and a second output node (Fig. 4: BLB) coupled to the second bit line; (Input and output nodes are interpreted to just be points on the bit line on either side of a repeater and therefore are inherent to any sram cell with bit lines.)
a pair of switches (Fig. 4: 402, 403) configured to couple to the first bit line (Fig. 4: BL) and the second bit line (Fig. 4: BLB) responsive to receiving an input signal (Fig. 4: PASS); and
a set of cross-coupled invertors (Fig. 4: 410) coupled to the pair of switches (Fig. 4: 402, 403), wherein the pair of switches and the set of cross-coupled invertors form a shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line) between the first bit line and the second bit line responsive to the input signal (Fig. 4: pass) being received by the pair of switches.
Based on the interpretation of the claims its assumed that a repeater is merely a SRAM cell configured to operate a certain way. There is a lack of structural language to differentiate it beyond the way its configured.
Regarding Claim 16, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein the plurality of memory cells (Fig. 4: 400) is connected in series to the pair of bit lines driven by the pair of BL drivers (Fig. 11A: 1156, 1157), respectively.
Regarding Claim 17, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein each repeater (Fig. 4: 400) of the plurality of repeaters is connected, via the respective shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line), to the pair of bit lines so that no break is made in a signal path of each of the pair of bit lines for inserting the plurality of repeaters in series with the plurality of memory cells and each repeater of the plurality of repeaters does not need to be bypassed or disabled during memory read operations. (Fig. 4: 402, 403; the pass gates shown in this figure show that the bit lines allow for the bit line connection such that no break is made in the signal path and thus there is no need to bypass or disable the cells connected to the bit line through the pass gate during the read operation.)
Regarding Claim 18, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein each repeater (Fig. 4: 400) of the plurality of repeaters is connected, via the respective shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line), as the differential signal can bypass each repeater of the plurality of repeaters when in the read mode, as the differential signal can transmit from the input nodes to the output nodes without being conducted by the set of cross-coupled inverters, the first switch, and the second switch.
(Fig. 4: 402, 403; disabling or enabling the pass gates allows for the cell to be bypass by the signal on the bit line such as when in read mode. Since the structure is identical to the one presented by applicant it would function the same way.)
Regarding Claim 19, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein the first switch (Fig. 4: 402) and the second switch (Fig. 4: 403) each includes a transmission gate formed using a PMOS transistor and an NMOS transistor connected in parallel (para 44 “Each pass gate 402, 403 is implemented using a PMOS device and an NMOS device connected in parallel.”), and
wherein drain and source terminals of the PMOS and NMOS transistors are connected (para 44 “Each pass gate 402, 403 is implemented using a PMOS device and an NMOS device connected in parallel.”), while gates of the PMOS and NMOS transistors are coupled to each other via an inverter (Fig. 4: PASS, PASSB).
Response to Arguments
Applicant's arguments filed July 7, 2026 have been fully considered but they are not persuasive.
Applicants arguments are largely semantic and/or relying on functional language rather than differentiating the structure of the disclosed apparatus from the prior art. Applicant states on page 16 paragraph 2 “Anticipation requires more than a statement that an SRAM cell could be configured to operate in a similar manner. The Office Action must identify in Bartling a repeater that is separate from, and not one of, the memory cells configured to store data, an uninterrupted bit-line signal path extending from the input node to the output node through the repeater, and a shunt connection whose components are isolated during read mode while a read signal propagates from the input nodes to the output nodes along the uninterrupted bit-line signal paths.”
Applicant is incorrect that showing an identical structure that is operated differently is alone insufficient as a basis for establishing anticipation. MPEP 2114(II) states “"[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.” Thus, since applicants claims are directed to apparatuses and not methods of operation or production, anticipating the structure alone is sufficient to form a basis for anticipation. Therefore, because Bartling anticipates the structure recited in Claims 1, 5, 9 and 15 the basis of anticipation is met. Failing to disclose a method of reading or writing a circuit as claimed by applicant is not a structural limitation and therefore does not need to be considered when forming a basis for anticipation.
Further applicant relies heavily on functional language to attempt to claim structural differences where there are none. For instance, the “uninterrupted bit-line signal path” claimed in Independent claims 1, 5, and 15 is merely a description of a typical bit line signal path, as the basic function of bit lines is to provide a continuous signal path that precharges in order to read or write any selected cells along the bit line. It is understood that unless otherwise stated that bit lines represent an uninterrupted signal path. Thus, the bit lines disclosed by Bartling are sufficient to meet the limitation of uninterrupted signal path. Similarly, the shunt connection described by applicant seems to describe how the connection to the bit line by the repeater behaves or what kind of connection it is rather anything having to do with that differentiates its structure. Thus, there is no reason to think that the SRAM cells disclosed by Bartling don’t also constitute a shunt connection as how they connect to the bit line is identical to the circuit disclosed by applicant.
Applicant further cannot differentiate the memory cells disclosed in their own application from their repeater circuit without using functional language. Applicant states in the office action and in the amendments to the claims that “memory cells configured to store data” as the way these cells are configured is their only differentiating factor from the repeater circuits which are not configured to store data. However no structural difference between the two is disclosed by applicant. Without disclosing a structure that shows that this configuration makes these apparatuses different there is no reason to assume that a “configuration” is anything other than a method of operating one vs the other.
Finally, applicant amended claims to include descriptions of read and write operations, which are plainly methods of operating the devices and have nothing to do with the structure. Method of operation is not sufficient to overcome anticipation when claiming apparatuses as applicant is doing in this application. See MPEP 2114(II).
For these reasons the rejections of Independent Claim 1, 5, and 15 under 35 U.S.C 102(a)(1) are maintained, as applicant has failed to over come the prior art taught By Bartling, which anticipates the claims disclosed by applicant.
Further upon further consideration the allowance of Claims 9 and 10 is corrected to be a rejection under 35 U.S.C. 102(a)(1). Claim 9 recites all the same structural limitations as independent claim 1. Additionally, the claim discusses the way the leading edge of a signal propagates through the bit line from one node to the next. MPEP 2112(II) states “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. "There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102." In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic. Therefore, a 35 U.S.C. 102 and 103 rejection is appropriate for these types of claims as well as for composition claims.” Because Bartling anticipates all the structural limitations of the claimed invention there is no reason to think that differential signals would not behave this way along the bit lines disclosed by Bartling. Therefore claims 9 and 10 are additional rejected under 35 U.S.C. 102(a)(1) after further consideration under continued examination.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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