DETAILED ACTION
This action is responsive to the following: the amendments to claims and drawings and arguments made in amendment filed December 29, 2025.
Claims 1-19 are pending. Claims 1, 5, 9, and 15 are independent. Claims 16-19 are new.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments to Claims and drawings filed on December 29, 2025 are entered. Claims 1-15 remain pending. Claims 16-19 are new and pending. Claim 9 is has been amended from a dependent to Independent claim and additional fees have been paid. The amendments overcome all of the objections set forth in the previous office action.
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9 states “to from go from” which is likely a typographic error that makes the claim language difficult to understand. Appropriate correction is required.
Claim Interpretation
The use of the terms “repeater,” ”input/output node,” ”shunt connection,” “intermediate node,” and “balance point” in claims 1-15 are being interpreted as follows:
“Repeater” is interpreted to be a 6T SRAM cell with NMOS pass gates or an 8T SRAM cell with transmission gate pass gates consisting of a NMOS and a PMOS in parallel. There is not structural difference between what is referred to as a “repeater” or “SRAM repeater” in the claims from a SRAM cell. The only difference in the claims is in the method of how it’s used but not in its structure.
“Input/output node” in refers to places on each bit line on either side of the repeater circuit. A node is commonly defined as a point where two wire or electronic components connect. The specification specifically states that benefit of the circuit in paragraph 44 is that “No signal path breaks may be included in memory column 702 using DCC repeat circuit 750.” Thus, within the context of this device there doesn’t appear to be a node but just a continuation of the bit line.
“Shunt Connection” is interpreted to be where the pass gate within the repeater circuit connect to the bit line. A shunt connection is normally understood to be defined as a “a device that is designed to provide a low-resistance path for an electrical current in a circuit.” And there does not appear to be any structural part of the circuit that would match that description so from context it assumed to be the connection to the bit line.
“Intermediate node” is interpreted to be an intermediate location on the bit line between structures. A node is commonly defined as a point where two wire or electronic components connect. The interpretation then follows that there seems to be no secondary electronic component or wire connecting to the bit line but rather just a location along bit line.
“Balance point” is interpreted to mean the same thing as intermediate and is just a location along the bit line.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 11-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bartling et al (US 20140210535 A1).
Regarding Independent Claim 1, Bartling teaches a memory array (Fig. 1: 110), comprising:
a plurality of memory cells (Fig. 4: 400) configured to store data;
a pair of bit line drivers (Fig. 11A: 1156, 1157) configured to provide a differential signal for writing data to at least some of the plurality of memory cells along a pair of bit lines (Fig. 11A: BL, BLB);
a sense amplifier (Fig. 8: 810) communicatively coupled to the bit line drivers to read data stored by at least some of the plurality of memory cells; and
a plurality of repeaters (Fig. 4: 400) connected in series to the plurality of memory cells, each repeater of the plurality of repeaters being connected, via a respective shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line), to the pair of BL drivers, wherein each repeater (Fig. 4: 400) of the plurality of repeaters comprises:
an input node (Fig. 4: BL, BLB) and an output node (Fig. 4: BL, BLB) along each bit line;
a set of cross-coupled inverters (Fig. 4: 410) configured to receive, regenerate, and output the differential signal;
a first switch (Fig. 4: 402) and a second switch (Fig. 4: 403) configured to provide the differential signal to the set of cross-coupled inverters when in write mode or bypass the set of cross-coupled inverters when in read mode (since this is a structural claim and applicant fails to outline what structures are unique to configure an SRAM cell this way its presumed that any standard SRAM cell could be configured that way.), and wherein:
the pair of bit lines (Fig. 4: BL, BLB) connect to the pair of BL drivers at a first node,
an intermediate node (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes) is placed along each bit line (Fig. 4: BL, BLB) between the first node and the input node of a first repeater of the plurality of repeaters, and
an additional intermediate node (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes) is placed along each bit line between the output node of a given repeater and the input node of a subsequent repeater.
Based on the interpretation of the claims its assumed that a repeater is merely a SRAM cell configured to operate a certain way. There is a lack of structural language to differentiate it beyond the way its configured.
Regarding Claim 2, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein the intermediate node (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes) and each additional intermediate node are placed at a balance point node (Fig. 4: BL, BLB; the balance point is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have balance points) of a respective bit line.
Regarding Claim 3, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein each repeater of the plurality of repeaters is:
a duty-cycle corrector (DCC) repeater comprising eight (8) transistors (Fig. 4: 410, 402, 403); or
an SRAM repeater comprising six (6) transistors (Fig. 4. 410, 403, 402).
Regarding Claim 4, Bartling teaches the limitations of Claim 3. Bartling further teaches the DCC repeater (Fig. 4: 400) includes the set of cross-coupled inverters (Fig. 4: 410) and a pair of transmission gates (Fig. 4: 402, 403) each including a PMOS transistor and an NMOS transistor; and
the SRAM repeater (Fig. 4: 400) includes the set of cross-coupled inverters (Fig. 4: 410) and a pair of transmission gates including an NMOS transistor (Fig. 4: 402, 403).
Regarding Independent Claim 5, Bartling teaches a repeater for a memory array, comprising:
a first input node coupled to a first bit line and a second input node coupled to a second bit line (Fig. 4: BL, BLB);
a first output node coupled to the first bit line and a second output node coupled to the second bit line (Fig. 4: BL, BLB);
a pair of switches configured to couple to the first bit line and the second bit line responsive to receiving an input signal (Fig 4: 402, 403); and
a set of cross-coupled invertors (Fig. 4: 410) coupled to the pair of switches, wherein the pair of switches (Fig 4: 402, 403) and the set of cross-coupled invertors (Fig. 4: 410) form a shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line) between the first bit line and the second bit line (Fig. 4: BL, BLB) responsive to the input signal (Fig. 4, PASS) being received by the pair of switches.
Based on the interpretation of the claims its assumed that a repeater is merely a SRAM cell configured to operate a certain way. There is a lack of structural language to differentiate it beyond the way its configured.
Regarding Claim 6, Bartling teaches the limitations of Claim 5. Bartling further teaches wherein the first input node and the second input node are coupled to a first intermediate node and a second intermediate node (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes), respectively, which are coupled to a first initial node and a second initial node, respectively, which are respectively coupled to a first bit line driver and a second bit line driver.
It is assumed that since the nodes as describe merely represent locations on a bit line as interpreted. That all the nodes are coupled to one another by virtue of all being part of the bit line.
Regarding Claim 7, Bartling teaches the limitations of Claim 6. Bartling further teaches wherein the first bit line driver (Fig. 11A: 1156) and the second bit line driver (Fig. 11A: 1157) are configured to output the input signal, the input signal being provided, via the first bit line (Fig. 11A: BL) and the second bit line (Fig. 11A: BL), respectively, to the first initial node and the second initial node, and the input signal (Fig. 11A: XOR_IN) also being provided to the pair of switches to cause the pair of switches couple to the first bit line and the second bit line, respectively.
It is assumed that since the nodes as describe merely represent locations on a bit line as interpreted. That all the nodes are coupled to one another by virtue of all being part of the bit line.
Regarding Claim 8, Bartling teaches the limitations of Claim 7. Bartling further teaches wherein the first intermediate node and the second intermediate node are placed at a first location along a portion of the first bit line and the second bit line between the first initial node and the first input node, wherein the first location is a balance point. (Fig. 4: BL, BLB; the intermediate node is interpreted as a location on the bit line. Therefore, the presence of bit lines is sufficient to show that they have intermediate nodes)
Regarding Claim 11, Bartling teaches the limitations of Claim 5. Bartling further teaches each switch of the pair of switches (Fig. 4: 402, 403) comprise a PMOS transistor and an NMOS transistor;
the repeater includes eight transistors (Fig. 4: 410, 402, 403); and
the repeater is a Duty-Cycle Corrector (DCC) repeater (Fig. 4: 400).
Regarding Claim 12, Bartling teaches the limitations of Claim 5. Bartling further teaches each switch of the pair of switches comprise an NMOS transistor (Fig. 4: 402, 403);
the repeater includes six transistors (Fig. 4; 402, 403, 410); and
the repeater is an SRAM repeater (Fig. 4: 402, 403, 410).
Regarding Claim 13, Bartling teaches the limitations of Claim 5. Bartling further teaches the first output node and the second output node are coupled to a memory cell (Fig: 1040), and the memory cell is coupled to an additional instance of the repeater. (Fig. 4: BL, BLB; all the nodes are interpreted as merely representing locations along the bit lines)
Regarding Claim 14, Bartling teaches the limitations of Claim 5. Bartling further teaches means (Fig. 1: 106) for reading data stored in a memory cell; and
means for writing data to a memory cell (Fig. 6: WRITE-0).
Regarding Independent Claim 15, Bartling teaches a cascading stack for a memory array (Fig. 10: 1040), comprising:
a plurality of memory cells (Fig. 4: 400); and
a plurality of repeaters (Fig. 4: 400), each coupled to a respective one of the plurality of memory cells (Fig. 10: 1041, 1040), wherein each repeater comprises (Fig. 4: 400):
a first input node (Fig. 4: BL) coupled to a first bit line and a second input node coupled to a second bit line (Fig. 4: BLB); (Input and output nodes are interpreted to just be points on the bit line on either side of a repeater and therefore are inherent to any sram cell with bit lines.)
a first output node (Fig. 4: BL) coupled to the first bit line and a second output node (Fig. 4: BLB) coupled to the second bit line; (Input and output nodes are interpreted to just be points on the bit line on either side of a repeater and therefore are inherent to any sram cell with bit lines.)
a pair of switches (Fig. 4: 402, 403) configured to couple to the first bit line (Fig. 4: BL) and the second bit line (Fig. 4: BLB) responsive to receiving an input signal (Fig. 4: PASS); and
a set of cross-coupled invertors (Fig. 4: 410) coupled to the pair of switches (Fig. 4: 402, 403), wherein the pair of switches and the set of cross-coupled invertors form a shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line) between the first bit line and the second bit line responsive to the input signal (Fig. 4: pass) being received by the pair of switches.
Based on the interpretation of the claims its assumed that a repeater is merely a SRAM cell configured to operate a certain way. There is a lack of structural language to differentiate it beyond the way its configured.
Regarding Claim 16, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein the plurality of memory cells (Fig. 4: 400) is connected in series to the pair of bit lines driven by the pair of BL drivers (Fig. 11A: 1156, 1157), respectively.
Regarding Claim 17, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein each repeater (Fig. 4: 400) of the plurality of repeaters is connected, via the respective shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line), to the pair of bit lines so that no break is made in a signal path of each of the pair of bit lines for inserting the plurality of repeaters in series with the plurality of memory cells and each repeater of the plurality of repeaters does not need to be bypassed or disabled during memory read operations. (Fig. 4: 402, 403; the pass gates shown in this figure show that the bit lines allow for the bit line connection such that no break is made in the signal path and thus there is no need to bypass or disable the cells connected to the bit line through the pass gate during the read operation.)
Regarding Claim 18, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein each repeater (Fig. 4: 400) of the plurality of repeaters is connected, via the respective shunt connection (Fig. 4: BL, BLB, 402, 403; connection of pass gates to bit line), as the differential signal can bypass each repeater of the plurality of repeaters when in the read mode, as the differential signal can transmit from the input nodes to the output nodes without being conducted by the set of cross-coupled inverters, the first switch, and the second switch.
(Fig. 4: 402, 403; disabling or enabling the pass gates allows for the cell to be bypass by the signal on the bit line such as when in read mode. Since the structure is identical to the one presented by applicant it would function the same way.)
Regarding Claim 19, Bartling teaches the limitations of Claim 1. Bartling further teaches wherein the first switch (Fig. 4: 402) and the second switch (Fig. 4: 403) each includes a transmission gate formed using a PMOS transistor and an NMOS transistor connected in parallel (para 44 “Each pass gate 402, 403 is implemented using a PMOS device and an NMOS device connected in parallel.”), and
wherein drain and source terminals of the PMOS and NMOS transistors are connected (para 44 “Each pass gate 402, 403 is implemented using a PMOS device and an NMOS device connected in parallel.”), while gates of the PMOS and NMOS transistors are coupled to each other via an inverter (Fig. 4: PASS, PASSB).
Allowable Subject Matter
Claims 9-10 are allowed.
Claim 9, the record or prosecution makes clear the reasons for allowance.
Claim 10, would be allowable for being dependent on claim 9.
Response to Arguments
Applicant's arguments filed December 29, 2025 have been fully considered but they are not persuasive.
Applicant correctly points out that the invocation of 35 U.S.C. 112(f) was improper and mistakenly invoked in the FAOM. Nevertheless, claim interpretation is still warranted as MPEP 2111 states claims ‘must be “given their broadest reasonable interpretation consistent with the specification.”’ Thus, the specific interpretations of the various terms from the claims based on the FAOM are still maintained.
Applicant argues the 102 rejection over Bartling is improper because the rejection identifies the BL/BLB as both the "pair of bit lines" and "shunt connection," and therefore, the "shunt connection" limitation is not satisfied. However, the shunt connection is understood to be the connection where the pass gate for the cell connects to the bit line. Thus, the Shunt connection is indeed anticipated by Bartling. Therefore, the rejection under 35 U.S.C 102(a)(1) is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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