DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 05/08/2024.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claim 1, Applicant claims a power supply comprising the following limitations, “when n is an integer more than or equal to 2 and i is an integer that is more than or equal to 1 and less than or equal to n−1 (see, lines 1-3)”, “first to n-th semiconductor switches (see, lines 4, 6-7)”, “first to n-th drive circuits (see, lines 6, 9-11, 14, 16)”, “i-th drive circuit (see, lines 18)”, “i-th semiconductor switch (see lines 19, 21-22, 25, 26, 29)”, “an (i-1)-th drive circuit (see line 20)”, “i-th to n-th semiconductor switches (see line 28-29, 33)”, “(i+1)-th to n-th semiconductor switches (see lines 30-31)”, and “an (i+1)-th drive circuit (see line 31)”, which is indefinite.
Table I
Scenario I:
When using Applicant’s claimed condition “n is an integer more than or equal to 2 (n≥2) and i is an integer that is more than or equal to 1 (i ≥1) and less than or equal to n−1 (i ≤ (n-1))”, results in following alternative interpretation (Scenario I): at least n must be equal to 2, which causes i to be equal to 1, leading to following interpretations of each claimed limitation(s),
first to n-th (i.e., 2) semiconductor switches: at least 1 to 2 semiconductor switches,
first to n-th (i.e., 2) drive circuits: at least 1 to 2 drive circuits,
i-th (i.e., 1) drive circuit: at least 1 drive circuit,
i-th (i.e., 1) semiconductor switch: at least 1 semiconductor switches,
an (i-1)-th (i.e., 1-1=0) drive circuit: zero or no drive circuit, in another word using no drive circuits or disabling all of them,
i-th (i.e., 1) to n-th (i.e., 2) semiconductor switches: at least 1 to 2 semiconductor switches,
(i+1)-th (i.e., 1+1=2) to n-th (i.e., 2) semiconductor switches: at least 2 to 2 semiconductor switches and
an (i+1)-th (i.e., 1+1=2) drive circuit: at least 2 drive circuits.
Scenario II:
When using Applicant’s claimed condition “n is an integer more than or equal to 2 (n≥2) and i is an integer that is more than or equal to 1 (i ≥1) and less than or equal to n−1 (i ≤ (n-1))”, results in following alternative interpretation (Scenario II): assuming n=3, which causes i=2, leading to following interpretations of each claimed limitation(s),
first to n-th (i.e., 3) semiconductor switches: at least 1 to 3 semiconductor switches,
first to n-th (i.e., 3) drive circuits: at least 1 to 3 drive circuits,
i-th (i.e., 2) drive circuit: at least 2 drive circuit,
i-th (i.e., 2) semiconductor switch: at least 2 semiconductor switches,
an (i-1)-th (i.e., 2-1=1) drive circuit: a driver circuit,
i-th (i.e., 2) to n-th (i.e., 3) semiconductor switches: at least 2 to 3 semiconductor switches,
(i+1)-th (i.e., 1+2=3) to n-th (i.e.,3) semiconductor switches: at least 3 to 3 semiconductor switches and
an (i+1)-th (i.e., 1+2=3) drive circuit: at least 3 drive circuits.
Based on above Scenario I-II’s explained interpretation, leads to following indefinite issues, as cited in note, by the Examiner.
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Claims 2-9 are depending from claim 1, inheriting same deficiencies and, thus rejected.
Allowable Subject Matter
Claims 1-9 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
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Above annotated Fig. 1, from Sankaran et al. (“Sankaran”, US Pat 5258446)
Regarding independent claim 1, Sankaran et al. (“Sankaran”, US Pat 5258446) teaches (Fig. 1-4; see above annotated Fig. 1 with citation) a power supply device (Fig. 1) comprising, when n is an integer more than or equal to 2 (n≥2) and i is an integer that is more than or equal to 1 (i ≥1) and less than or equal to n−1 (i ≤ (n-1)) (in another word, at least n must be equal to 2, which causes i to be equal to 1):
first to n-th semiconductor switches (14: transistor switch 17 formed using SW1-6) connected in series between first (input terminal 38, used by 17’s SW1-6’s input power line) and second (output terminal of 17’s SW1-6’s, used for load) terminals;
first to n-th drive circuits (plural gate drivers in 16) that are provided corresponding to the first to n-th semiconductor switches (14: transistor switch 17 formed using SW1-6), respectively, and drive the corresponding semiconductor switches (14: transistor switch 17 formed using SW1-6) in response to a control signal (any one of 18’s gating signal output 36);
an interface circuit (annotated interface circuit receives gating line 36 from 18 and various sensed signal from 17. Taught interface circuit generates various state detection signals ‘28, 30’ and various abnormality detection signals ‘80’s output 24, 82’s output 32, 84’s output 34 &/or 86’s output 26’ to 18 and plural gate drivers in 16) that transmits (taught interface circuit’s generated signals) and receives (taught interface circuit’s received signals) signals to and from the first to n-th drive circuits (plural gate drivers in 16); and
first and second communication lines (any two communication lines of the plural communication lines being first and second communication lines) that connect the interface circuit (annotated interface circuit receives gating line 36 from 18 and various sensed signal from 17. Taught interface circuit generates various state detection signals ‘28, 30’ and various abnormality detection signals ‘80’s output 24, 82’s output 32, 84’s output 34 &/or 86’s output 26’ to 18 and plural gate drivers in 16) and the first to n-th drive circuits (plural gate drivers in 16) in series, wherein the first communication line (any two communication lines of the plural communication lines being first and second communication lines) is configured to sequentially transmit the control signal (any one of 18’s gating signal output 36) from the interface circuit (annotated interface circuit receives gating line 36 from 18 and various sensed signal from 17. Taught interface circuit generates various state detection signals ‘28, 30’ and various abnormality detection signals ‘80’s output 24, 82’s output 32, 84’s output 34 &/or 86’s output 26’ to 18 and plural gate drivers in 16) to the n-th drive circuit (plural gate drivers in 16) via the first drive circuit (i.e., any one selected driver in 16 can be first driver circuit), the second communication line (any two communication lines of the plural communication lines being first and second communication lines) is configured to sequentially transmit a state detection signal (various state detection signals ‘ gate Vth(s) 28, sensed voltage (V) & current (I) feedback (FB) signal 30’) indicating an operation state (various state detection signals ‘ gate Vth(s) 28, sensed voltage (V) & current (I) feedback (FB) signal 30’) of the semiconductor switches (14: transistor switch 17 formed using SW1-6), from the n-th drive circuit (plural gate drivers in 16) to the interface circuit (taught interface circuit) via the first drive circuit (i.e., any one selected driver in 16 can be first driver circuit),
an i-th drive circuit (i.e., any another selected driver in 16 can be i-th driver circuit) includes a driver (i.e., any another selected driver in 16 can be i-th driver circuit, in another word “a driver”) that drives an i-th semiconductor switch (i.e., SW1) in response to the control signal (any one of 18’s gating signal output 36) received from … drive circuit (plural gate drivers in 16), an abnormality detection circuit (various abnormality detection signals ‘80’s output 24, 82’s output 32, 84’s output 34 &/or 86’s output 26’ to 18 and plural gate drivers in 16) for detecting an abnormality of the i-th semiconductor switch (SW1), and first and second notification members (any two various abnormality detection signals ‘80’s output 24, 82’s output 32, 84’s output 34 &/or 86’s output 26’ to 18 and plural gate drivers in 16, when received by 18, can be interpreted as first and second notification members), and
the abnormality detection circuit (various abnormality detection signals ‘80’s output 24, 82’s output 32, 84’s output 34 &/or 86’s output 26’ to 18 and plural gate drivers in 16) detects the abnormality of the i-th semiconductor switch (SW1) based on the control signal (any one of 18’s gating signal output 36) and an operation state (various state detection signals ‘gate Vth(s) 28, sensed voltage (V) & current (I) feedback (FB) signal 30’) of the i-th semiconductor switch (SW1).
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Fig. 2
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Above Fig. 2-3, from Wilson et al. (“Wilson”, US Pub 2017/0244241); Para 17-27
Wilson et al. (“Wilson”, US Pub 2017/0244241) teaches a power supply device (Fig. 2-3) comprising, when n is an integer more than or equal to 2 (n≥2) and i is an integer that is more than or equal to 1 (i ≥1) and less than or equal to n−1 (i ≤ (n-1)) (in another word, at least n must be equal to 2, which causes i to be equal to 1):
first to n-th semiconductor switches (first to fourth switches 108 being shown, could be even more “108(s)”) connected in series between first (input terminal being left hand side of Fig. 2) and second (output terminal being right hand side of Fig. 2) terminals;
first to n-th drive circuits (timer 112’s output used by plural drivers LED 114, to drive respective switches 107) that are provided corresponding to the first to n-th semiconductor switches (108(s)), respectively, and drive the corresponding semiconductor switches in response to a control signal (timer 112’s output);
an interface circuit (input-&-output side selection switches 122, input-&-output side filters 118, input-&-output side current sources 124, input-&-output side shorting switches 120 and input-&-output side thresholds 126) that transmits and receives signals (i.e., via plural respective use of fiber optical links ‘132, 130’ and other arrowed signal lines) to and from the first to n-th drive circuits (timer 112’s output used by plural drivers LED 114, to drive respective switches 107); and
first and second communication lines (i.e., via plural respective use of fiber optical links ‘132, 130’) that connect the interface circuit (input-&-output side selection switches 122, input-&-output side filters 118, input-&-output side current sources 124, input-&-output side shorting switches 120 and input-&-output side thresholds 126) and the first to n-th drive circuits (timer 112’s output used by plural drivers LED 114, to drive respective switches 107) in series, wherein the first communication line (i.e., via plural respective use of fiber optical links ‘132, 130’) is configured to sequentially transmit the control signal (timer 112’s output) from the interface circuit (input-&-output side selection switches 122, input-&-output side filters 118, input-&-output side current sources 124, input-&-output side shorting switches 120 and input-&-output side thresholds 126) to the n-th drive circuit (timer 112’s output used by plural drivers LED 114, to drive respective switches 107) via the first drive circuit (LED1), the second communication line (i.e., via plural respective use of fiber optical links ‘132, 130’) is configured to sequentially transmit a state detection signal (i.e., 120) indicating an operation state (short-circuit sensed state) of the semiconductor switches (108s), from the n-th drive circuit (timer 112’s output used by plural drivers LED 114, to drive respective switches 107) to the interface circuit (input-&-output side selection switches 122, input-&-output side filters 118, input-&-output side current sources 124, input-&-output side shorting switches 120 and input-&-output side thresholds 126) via the first drive circuit (LED1), an abnormality detection circuit (current fault & limiting operation, abstract) for detecting an abnormality of the i-th semiconductor switch (selected at least one of 108(s)), and first (i.e., any one of 184’s output) and second (i.e., any another one of 184’s output) notification members.
However, none of the cited prior art teaches specific & sequential control, as follows, “an i-th drive circuit includes a driver that drives an i-th semiconductor switch in response to the control signal received from an (i−1)th drive circuit, an abnormality detection circuit for detecting an abnormality of the i-th semiconductor switch, and first and second notification members, and the abnormality detection circuit detects the abnormality of the i-th semiconductor switch based on the control signal and an operation state of the i-th semiconductor switch, and notifies a detection result using the first notification member, generates the state detection signal indicating an operation state of the i-th to n-th semiconductor switches based on the operation state of the i-th semiconductor switch and the state detection signal indicating an operation state of (i+1)-th to the n-th semiconductor switches received from an (i+1)-th drive circuit, and detects a mismatch between the control signal and the operation state of the i-th to n-th semiconductor switches based on the control signal and the generated state detection signal, and notifies a detection result using the second notification member.
Claims 2-9 are depending from claim 1.
Conclusion
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/NUSRAT QUDDUS/Examiner, Art Unit 2838