DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-19 are objected to because of the following informalities:
All abbreviations (RF, GNSS, NS2CS, etc.) should be spelled out upon their first appearance in the claims.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1 lines 9-10, it is unclear which digitized signals are converted into low-bit data by the plurality of re-quantizers – the digitized signals that are produced by the ADCs in lines 6-7, or the digitized signals that have been processed by the signal processors in line 8. Examiner recommends amending the language for clarity, for example “a plurality of re-quantizers configured to convert the processed digitized signals into low-bit data” if it is the processed digital signals in line 8 that are meant.
Regarding claim 1 line 11, it is unclear how “a plurality of interface blocks NS2CS configured to generate packages” relates to the preceding claim limitations. According to para. [0051] “a package is the number of samples assigned or set by CPU 107. Samples are data over one clock period. Service information or additional information can be added to the package”. However the interface blocks NS2CS have not been recited as receiving any data with which packages could be generated. Is the low-bit data recited in lines 9-10 used to generate packages, or some other data? Examiner recommends clarifying the relationship between the interface blocks NS2CS and the preceding limitations.
Regarding claim 1 line 12, the scope of “a plurality of interface blocks C2N” cannot be clearly determined, as the term “C2N” is not used in the specification or elsewhere in the claims. Examiner notes that the specification and subsequent claims appear to use the term “CS2NS” for this feature.
Regarding claim 1 lines 14-17, the scope of “the data, from outputs of the plurality of ADCs, the signal processors and the re-quantizers to inputs of interface blocks NS2CS, and from output of interface blocks CS2NS” cannot be clearly determined, as “the data” lacks clear antecedent basis in the claim. Only the “plurality of re-quantizers configured to convert the digitized signals into low-bit data” (lines 9-10), and “plurality of interface blocks C2N configured to convert the packages into data” (lines 12-13) have been previously recited as providing data, and the claim does not previously recite any “interface blocks CS2NS” from which data can be output. Examiner recommends amending the claim to use consistent language.
Regarding claim 1 line 20, “the plurality of channels” lack antecedent basis in the claim.
Regarding claim 1 line 23, “the data” lacks clear antecedent basis in the claim for the same reasons discussed above with respect to lines 14-17.
Regarding claim 1 line 27, it is unclear if “a plurality of channels” are meant to refer to “the plurality of channels” recited in line 20 or to some other channels.
Regarding claim 1 lines 35-36, “the plurality of channels that are configured to process data from the navigation DMA or AFIFO” lack clear antecedent basis in the claim.
Regarding claim 4 lines 3-4, “into one package of a designated size transmission to memory for the Navigation DMA” is ungrammatical and its scope cannot be clearly determined.
Regarding claim 5, it is unclear why the NC2CS has been recited as performing the function “decimate the digitized signal and re-quantize the decimated signal into low bit data”, as claim 1 lines 9-10 already recite low bit data being generated by a plurality of re-quantizers.
Regarding claim 9 lines 1-2, “the data readiness” lacks antecedent basis and it is unclear what is meant. Paras. [0019] and [0023] of the specification describe a “data readiness flag signal”. Amending the language to “a data readiness flag signal” may help. Further, it is unclear what processing is referred to by “after data processing”.
Regarding claim 12 line 2, “the package” lacks clear antecedent basis. The claim previously refers only to a plurality of packages – see claim 1 lines 11, 12, 21, 23, and 25.
Regarding claim 14 line 1, “the interface blocks CS2NS” lack antecedent basis in the claim. Claim 1 provides basis only for “interface blocks NS2CS” and “interface blocks C2N”.
Regarding claim 15 lines 1-2, it is unclear what is meant by “the interface blocks CS2NS... starts to send the data, and when receiving data ends, generates an interrupt request transmitted to the CPU” (emphasis added). In view of para. [0040] of the specification “In one embodiment, interface block CS2NS 203 transmits data from memory 109 to Navigation system 200 via BUS 108. When the transmit operation is over, interface block CS2NS 202 interrupts operation of CPU 107” (emphasis added), it appears that “when receiving data ends” may be more clearly expressed as “when transmitting data ends” or similar.
Regarding claim 19, the scope of “wherein signal processing chains can be assembled from any combination of components comprising a CPU, a signal processor, interface blocks NS2CS, interface blocks CS2NS, re-quantizers, hardware accelerators, AFIFO, navigation DMA, and navigation Channels” cannot be clearly determined. The claim does not previously recite any signal processing chains, and it is unclear how any such chains would relate to the previously recited elements. Further, the scope of the language appears to include, for example, a chain comprising only CPU and an interface block CS2NS. Such a chain would not be sufficient to perform the functions performed in claim 1. Examiner cannot determine what Applicant intends to encompass with this claim language.
The remaining claims are dependent.
Allowable Subject Matter
Claims 1-19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
Regarding claim 1, the closest prior art (Applicant’s Fig. 1 and corresponding paras. [0019]-[0023], which comprise admitted prior art in view of para. [0004] “Fig. 1 shows a prior art Global Navigation Satellite System (GNSS) Receiver”) teaches a navigation receiver comprising:
a plurality of RF paths configured to receive GNSS signals from an antenna and transmit the GNSS signals in a frequency range for digitizing the GNSS signals (Fig. 1 “From RF Path”; para. [0020] “The RF paths, in one embodiment, are configured to transmit the GNSS signals in a particular frequency range for digitization”);
a navigation system (100, Fig. 1) configured to process the GNSS signals based on clock CLKnav (para. [0024] “CLKnav”), the navigation system comprising:
a plurality of analog to digital convertors (ADC) configured to digitize signals from the plurality of RF paths (ADC(1)...(A), Fig. 1);
a plurality of signal processors configured to process the digitized signals (Signal Processor 102(1,1)... 102(1,P), Fig. 1);
a time control configured to adjust a time scale to generate a tick signal (Time Control 105, Fig. 1);
a CPU system (CPU System 110, Fig. 1) comprising a memory (Memory 109, Fig. 1) and a CPU (CPU 107, Fig. 1).
PNG
media_image1.png
564
778
media_image1.png
Greyscale
In addition, Riley (US 20090207075 A1, cited on IDS) teaches requantizers configured to convert digitized signals into low-bit data (decimators 550, Fig. 5) in order to provide power savings (para. [0045]), and An (US 20100194635 A1) teaches that, in conventional GPS systems, “Hardware accelerators have been essential to meeting the high computational requirements of known GPS decoding techniques” (para. [0023]).
It would have been obvious to modify Applicant’s admitted prior art in view of Riley and An by implementing requantizers and hardware accelerators in order to provide power savings and meet high computational requirements.
However the prior art does not teach or make obvious the combination:
a plurality of interface blocks NS2CS configured to generate packages;
a plurality of interface blocks C2N configured to convert the packages into data;
a MUX interconnect configured to distribute the data, from outputs of the plurality of ADCs, the signal processors and the re-quantizers to inputs of interface blocks NS2CS, and from outputs of interface blocks CS2NS to the plurality of signal processors and the plurality of re-quantizers;
a time control configured to adjust a time scale to generate a tick signal;
an asynchronous first-in first-out (AFIFO) configured to send the low-bit data and the tick signal to the plurality of channels for processing; and
a CPU System configured to process the packages based on clock CLKcpu, the CPU system comprising:
a memory configured to store the data and the packages;
a plurality of hardware accelerators configured to process the packages;
a navigation DMA configured to convert the packages into data for a plurality of channels;
a commutator configured to select data from the navigation DMA; and
a CPU configured to synchronize control between the plurality of signal processors, the plurality of re-quantizers, interface blocks NS2CS, interface blocks CS2NS, the plurality of hardware accelerators, and the navigation DMA based on the tick signal, and configured to control the navigation system and the CPU system, read and process a result of GNSS signal processing from the plurality of channels that are configured to process data from the navigation DMA or AFIFO,
wherein an operation frequency of the navigation DMA and the plurality of channels is synchronous and equal to or greater than the clock CLKcpu.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSI J GALT whose telephone number is (571)270-1469. The examiner can normally be reached Monday-Friday, 9AM - 5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KELLEHER can be reached at (571)27. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CASSI J GALT/Primary Examiner, Art Unit 3648