DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 4, 6-8, and 11-15 are pending in this application.
Response to Amendment
Claims 1, 3, 4, 6-8, 11, and 12 are amended. Claims 2, 5, 9, and 11 are canceled.
Response to Arguments
Applicant's arguments filed 07/15/2026 have been fully considered but they are not persuasive. In regard to claim 1, Applicant argues that Lou Chinese Patent Document CN 103928444A (hereinafter “Lou”) teaches two diodes for each of the first and second static electricity conducting components and the amended claim 1 recites three transistors for each of the first and second static electricity conducting components. However, Lou discloses in [0049] and figures 4a and 4b that the diodes can be equivalent diodes formed by transistors; therefore, Lou discloses transistors. Furthermore, Lou discloses in [0047] that two stages are shown, but the number of stages is not limited; therefore, Lou discloses the use of any number of transistors which includes three. Therefore, this is not persuasive. In regard to claim 8, Applicant argues that Tsai et al. U.S. Patent Application 2006/0279667 (hereinafter “Tsai”) does not teach at least one end of the at least one electrostatic transmission line being directly coupled to at least one of the at least one ground terminal. However, Tsai teaches the common electrode 33 in figure 5 (i.e. the ground terminal) connected to the ESD line in the figure below. Therefore, this is not persuasive.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 4, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin Chinese Patent Document CN 107863340 A (hereinafter “Jin”) and further in view of Lou Chinese Patent Document CN 103928444 A (hereinafter “Lou”).
Regarding claim 1, Jin teaches an electrostatic discharge circuit (refer to first and second electrostatic protection circuits 2a and 2b)(figs.2, 10, and 12), comprising: a first static electricity conducting component (i.e. transistor T1)(figs. 10 and 12), coupled between a first signal terminal (i.e. signal line 5c1)(fig.12) and a second signal terminal (i.e. signal line 5c2)(fig.12); wherein the first static electricity conducting component is configured to: based on that an absolute value of a first voltage difference between the first signal terminal and the second signal terminal is less than a first threshold voltage, disconnect the first signal terminal from the second signal terminal (implicit)( transistor T1 acts like a diode with the cathode connected to the first signal terminal and the anode connected to the second signal terminal, when the voltage difference is equal to or less than the inherent turn-off threshold/voltage of the transistor/diode, the transistor does not conduct – i.e. the signal terminals are disconnected); and based on that a potential of the first signal terminal is less than a potential of the second signal terminal, and an absolute value of a second voltage difference between the first signal terminal and the second signal terminal is greater than a second threshold voltage, rise the potential of the first signal terminal and lower the potential of the second signal terminal (implicit)(transistor T1 acts like a diode with the cathode connected to the first signal terminal and the anode connected to the second signal terminal, when the potential difference exceeds the turn-on voltage/threshold, transistor T1 will conduct to equalize the voltage between the two signal lines); wherein the second threshold voltage is greater than or equal to the first threshold voltage (inherent)(the first threshold is equivalent to the turn-off threshold of the transistor/diode and the second threshold is equivalent to the turn-on threshold of the transistor/diode; the turn-on threshold must be equal to or greater than the turn-off threshold or the transistor/diode will not work); and a second static electricity conducting component (i.e. transistor T2)(figs. 10 and 12), coupled between the first signal terminal and the second signal terminal (implicit)(refer to figs.10 and 12), wherein the second static electricity conducting component is configured to: based on that the absolute value of the first voltage difference between the first signal terminal and the second signal terminal is less than the first threshold voltage, disconnect the first signal terminal from the second signal terminal (implicit)(transistor T2 acts like a diode with the anode connected to the first signal terminal and the cathode connected to the second signal terminal, when the voltage difference is equal to or less than the inherent turn-off threshold/voltage of the transistor/diode, the transistor does not conduct – i.e. the signal terminals are disconnected); and based on that the potential of the first signal terminal is greater than the potential of the second signal terminal, and the absolute value of the second voltage difference between the first signal terminal and the second signal terminal is greater than the second threshold voltage, lower the potential of the first signal terminal and rise the potential of the second signal terminal (implicit)(transistor T2 acts like a diode with the cathode connected to the first signal terminal and the anode connected to the second signal terminal, when the potential difference exceeds the turn-on voltage/threshold, transistor T2 will conduct to equalize the voltage between the two signal lines); however, Jin does not teach wherein the first static electricity conducting component comprises: 3 first transistors connected in series in sequence; in the 3 first transistors, a second electrode of a first transistor at a first position is coupled to the first signal terminal, a first electrode of a first transistor at an m-th position is coupled to a second electrode of a first transistor at an (m+1)-th position, and a first electrode of a first transistor at a third position is coupled to the second signal terminal; wherein 1 ≤ m ≤ 3, and m is an integer; wherein the second static electricity conducting component comprises: 3 second transistors connected in series in sequence; and in the 3 second transistors, a first electrode of a second transistor at a first position is coupled to the first signal terminal, a second electrode of a second transistor at an n-th position is coupled to a first electrode of a second transistor at a (n+1)-th position, a second electrode of a second transistor at a third position is coupled to the second signal terminal; wherein 1 ≤ n ≤ 3, and n is an integer. However, Lou teaches wherein the first static electricity conducting component comprises: 3 first transistors (refer to second diode group 34)(fig.3b)(refer also to figs.4a and 4b and [0047]: “Referring to fig. 3b, a schematic diagram of a two-stage esd device structure provided for the embodiment of the present application includes a first diode group 33 and a second diode group 34, where the first diode group 33 and the second diode group 34 each include two diodes connected in series, an anode of the first diode group 33 is connected to a cathode of the second diode group 34, the anode of the first diode group 33 further serves as one connection terminal of the two-stage esd device, the cathode of the first diode group 33 is connected to the anode of the second diode group 34, and the cathode of the first diode group 33 further serves as the other connection terminal of the two-stage esd device. It should be noted that the present embodiment does not limit the number of stages of the electrostatic discharge device, and the number of stages of the electrostatic discharge device mentioned in the present embodiment is only an example, and is not limited.” and [0049]: “More preferably, the diode constituting the electrostatic discharge device may be an equivalent diode formed by connecting the drain and gate of the TFT transistor, and specifically, referring to fig. 4a, the equivalent diode formed by the N-type TFT transistor is shown in a connection diagram, where the drain D and gate G of the N-type TFT transistor are connected to be equivalent to the anode of the diode, and the source S is equivalent to the cathode of the diode. Referring to fig. 4b, it is a connection diagram of an equivalent diode formed by a P-type TFT transistor, in which the drain D and the gate G of the P-type TFT transistor are connected to be equivalent to the cathode of the diode, and the source S is equivalent to the anode of the diode.”) connected in series in sequence (implicit)(refer to D1 and D2 in the figure below)(fig.3b); in the 3 first transistors, a second electrode of a first transistor (refer to the cathode of D1 in the figure below)(fig.3b)(refer also to source S of the NMOS transistor)(fig.4a)(refer also to drain D of the PMOS transistor)(fig.4b) at a first position (implicit) is coupled to the first signal terminal (implicit)(refer to T1 in the figure below)(fig.3b), a first electrode of a first transistor at an m-th position (refer to the anode of D1 in the figure below)(fig.3b)(refer also to drain D of the NMOS transistor)(fig.4a)(refer also to source S of the PMOS transistor)(fig.4b) is coupled to a second electrode of a first transistor at an (m+1)-th position (refer to the cathode of D2 in the figure below)(fig.3b)(refer also to source S of the NMOS transistor)(fig.4a)(refer also to drain D of the PMOS transistor)(fig.4b), and a first electrode of a first transistor at a third position (refer to the anode of D2 in the figure below)(fig.3b)(refer also to drain D of the NMOS transistor)(fig.4a)(refer also to source S of the PMOS transistor)(fig.4b) is coupled to the second signal terminal (refer to T2 in the figure below)(fig.3b); wherein 1 ≤ m ≤ 3, and m is an integer (implicit); wherein the second static electricity conducting component comprises: 3 second transistors (refer to first diode group 33)(fig.3b)(refer also to figs.4a and 4b and [0047] and [0049]) connected in series in sequence (implicit)(refer to D3 and D4 in the figure below)(fig.3b); in the 3 second transistors, a first electrode of a second transistor (refer to the anode of D3 in the figure above)(fig.3b)(refer also to drain D of the NMOS transistor)(fig.4a)(refer also to source S of the PMOS transistor)(fig.4b) at a first position (implicit) is coupled to the first signal terminal (implicit)(refer to T1 in the figure above)(fig.3b), a second electrode of a second transistor at an n-th position (refer to the cathode of D3 in the figure above)(fig.3b)(refer also to source S of the NMOS transistor)(fig.4a)(refer also to drain D of the PMOS transistor)(fig.4b) is coupled to a first electrode of a second transistor at an (n+1)-th position (refer to the anode of D4 in the figure below)(fig.3b)(refer also to drain D of the NMOS transistor)(fig.4a)(refer also to source S of the PMOS transistor)(fig.4b), a second electrode of a second transistor at a third position (refer to the cathode of D4 in the figure above)(fig.3b)(refer also to source S of the NMOS transistor)(fig.4a)(refer also to drain D of the PMOS transistor)(fig.4b) is coupled to the second signal terminal (refer to T2 in the figure below)(fig.3b); wherein 1 ≤ n ≤ 3, and n is an integer (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Jin to include the three transistors in series of Lou to provide the advantage of properly sizing the threshold voltage of the transistors to the circuit requirements (refer to Lou [0047] and [0048]).
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Regarding claim 3. Jin and Lou teach the electrostatic discharge circuit according to claim 1, wherein all first transistors in the first static electricity conducting component are P-type transistors (refer to Jin page 8 lines 3-5)(refer also to Lou figure 4b), and a second electrode (i.e. Lou drain D)(fig.4b) and a gate of the first transistor (i.e. Lou gate G)(fig.4b) are coupled to each other (implicit)(refer to Lou fig.4b).
Regarding claim 4, Jin and Lou teach the electrostatic discharge circuit according to claim 1, wherein all first transistors in the first static electricity conducting component are N-type transistors (refer to Jin page 8 lines 3-5)(refer also to Lou figure 4a), and a first electrode (i.e. Lou drain D)(fig.4a) and a gate of the first transistor (i.e. Lou gate G)(fig.4a) are coupled to each other (implicit)(refer also to Jin figures 10 and 12) .
Regarding claim 6, Jin and Lou teach the electrostatic discharge circuit according to claim 1, wherein all second transistors in the second static electricity conducting component are P-type transistors (refer to Jin page 8 lines 3-5)(refer also to Lou figure 4b), and a second electrode (i.e. Lou drain D)(fig.4b) and a gate of the second transistor (i.e. Lou gate G)(fig.4b) are coupled to each other (implicit)(refer to Lou fig.4b).
Regarding claim 7, Jin and Lou teach the electrostatic discharge circuit according to claim 1, wherein all second transistors in the second static electricity conducting component are N-type transistors (refer to Jin page 8 lines 3-5)(refer also to Lou figure 4a), and a first electrode (i.e. Lou drain D)(fig.4a) and a gate of the first transistor (i.e. Lou gate G)(fig.4a) are coupled to each other (implicit)(refer also to Jin figures 10 and 12).
Claim(s) 8, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin and Lou as applied to claim 1 above, and further in view of Tsai et al. U.S. Patent Application 2006/0279667 (hereinafter “Tsai”).
Regarding claim 8, Jin and Lou teach an array substrate (refer to Jin abstract and claim 1), comprising: a base substrate (refer to Jin claim 19); a plurality of pixels (i.e. Jin pixel electrodes 6)(fig.2) on the base substrate (implicit); wherein at least one of the plurality of pixels comprises a pixel circuit (i.e. Jin switch transistor 7 and transistor 3)(fig.2); a plurality of signal lines (i.e. Jin lines 5a, 5b, and 5c)(fig.2) on the base substrate (implicit); wherein the pixel circuit of the at least one of the plurality of pixels is coupled to at least one of the plurality of signal lines (implicit)(refer to Jin fig.2); and a plurality of electrostatic discharge circuits (i.e. Jin electrostatic protection circuits 2, 2a, and 2b)(fig.2) according to claim 1 on the base substrate (implicit)(refer to the rejection of claim 1 above); wherein a first signal terminal of any one of the plurality of electrostatic discharge circuits is coupled to one of the plurality of signal lines (implicit)(refer to Jin figs 2, 10, and 12), and a second signal terminal of the any one of the plurality of electrostatic discharge circuits is coupled to another one of the plurality of signal lines (implicit)(refer to Jin figs 2, 10, and 12); and two signal lines connected with a same electrostatic discharge circuit are arranged adjacent to each other (implicit)(refer to figs 2, 10, and 12), wherein the array substrate comprises a display region (i.e. Jin display area 1)(fig.2)(refer to also to Jin claim 1: “display region”) and a peripheral region (refer to Jin area outside of display area 1)(fig.2)(refer also to Jin claim 1: “non-display region”); wherein the plurality of pixels and the plurality of signal lines are located in the display region (implicit)(refer to Jin fig.2); and the plurality of electrostatic discharge circuits are located in the peripheral region (implicit)(refer to Jin fig.2); wherein the peripheral region further comprises: at least one electrostatic transmission line (i.e. Jin common voltage signal line 4b)(fig.2); and the at least one electrostatic transmission line is coupled to at least one of the plurality of signal lines via at least one of the plurality of electrostatic discharge circuits (implicit)(refer to Jin electrostatic protection circuit 2b)(fig.2); however, Jin and Lou do not teach at least one ground terminal; at least one end of the at least one electrostatic transmission line is coupled to at least one of the at least one ground terminal. However, Tsai teaches at least one ground terminal (i.e. common electrode 33)(fig.5); at least one end of the at least one electrostatic transmission line is coupled to at least one of the at least one ground terminal (implicit)(refer to ESD line in the figure above)(fig.5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the array substrate of Jin and Lou to include the terminals of Tsai to provide the advantage of facilitating connection of the electrostatic transmission line to a device ground or another array substrate.
Regarding claim 12, Jin, Lou, and Tsai teach the array substrate according to claim 8, wherein the peripheral region further comprises: a plurality of signal transmission terminals (refer to Tsai pads Data N through Data N+4)(fig.5) located at first ends of the plurality of signal lines (implicit)(refer to Tsai signal lines in the figure above)(fig.5); wherein the first end of each of the plurality of signal lines is coupled to at least one of the plurality of signal transmission terminals (implicit); and the at least one ground terminal is located at at least one side of the plurality of signal transmission terminals (implicit), and the at least one electrostatic transmission line extends from a side of the plurality of signal transmission terminals to the other side of the plurality of signal transmission terminals (implicit).
Regarding claim 13, Jin, Lou, and Tsai teach the array substrate according to claim 12, wherein the plurality of electrostatic discharge circuits are located between a region where the plurality of signal transmission terminals are located and a region where the plurality of signal lines are located (implicit)(refer to Tsai ESD protection units 30)(fig.5).
Regarding claim 14, Jin, Lou, and Tsai teach the array substrate according to claim 8, wherein the signal lines comprise data signal lines (i.e. Jin data line 5b)(fig.2); wherein pixel circuits in one column of pixels are coupled to at least one data signal line of the plurality of signal lines (implicit); however, they do not teach wherein the first voltage difference is a voltage difference between a data voltage corresponding to a maximum grayscale and a data voltage corresponding to a minimum grayscale loaded on the data signal line. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have the first voltage difference is a voltage difference between a data voltage corresponding to a maximum grayscale and a data voltage corresponding to a minimum grayscale loaded on the data signal line, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the array substrate of Jin, Lou, and Tsai to include wherein the first voltage difference is a voltage difference between a data voltage corresponding to a maximum grayscale and a data voltage corresponding to a minimum grayscale loaded on the data signal line to provide the advantage of ensuring the static electricity conducting components do not conduct when normal working voltages and voltage differences are present on the signal lines, thereby preventing unnecessary downtime.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin, Lou, and Tsai as applied to claim 8 above, and further in view of Xiao et al. U.S. Patent Application 2022/0052036 (hereinafter “Xiao”).
Regarding claim 11, Jin and Tsai teach the array substrate according to claim 10; however, they do not teach wherein the at least one electrostatic transmission line is arranged around the plurality of pixels. However, Xiao teaches wherein the at least one electrostatic transmission line is arranged around the plurality of pixels (refer to discharge electrode 30)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the array substrate of Jin, Lou, and Tsai to include the arrangement of the electrostatic transmission line of Xiao to provide the advantage of facilitating connection of the electrostatic transmission line to the pixels through the discharge circuits while minimizing wiring.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin as applied to claim 8 above, and further in view of Tang et al. U.S. Patent Application 2019/0384084 (hereinafter “Tang”).
Regarding claim 15, Jin, Lou, and Tsai teach a display apparatus (refer to Jin abstract), comprising an array substrate according to claim 8 (refer to the rejection of claim 8 above); however, they do not teach the apparatus comprising a plurality of array substrates, wherein the plurality of array substrates are spliced together. However, Tang teaches the apparatus comprising a plurality of array substrates (refer to abstract), wherein the plurality of array substrates are spliced together (refer to abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify then display apparatus of Jin, Lou, and Tsai to include the multiple spliced array substrates of Tang to provide the advantage of allowing for the manufacture of larger displays (refer to Tang [0003]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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