DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1, in lines 9-10, recites the limitation “…the interconnection bus is configured to adjust an input and output relationship between each operation unit according to an instruction of the processor.”, which is not clear and confusing, since a bus is not a configurable device/controller/processor. Applicants are required to make the necessary amendment in reply to this office action.
Claim 7, in lines 9-10, recites the limitation “…adjusting, by an interconnection bus, an input and output relationship between each operation unit according to the routing information,…”, which is not clear and confusing, since a bus is not a configurable device/controller/processor. Applicants are required to make the necessary amendment in reply to this office action.
Claim 9, in lines 3-4, recites the limitation “…adjusting, by the interconnection bus, the input and output relationship between each internal unit of each operation unit.”, which is not clear and confusing, since a bus is not a configurable device. Applicants are required to make the necessary amendment in reply to this office action. Furthermore, claim 9 recites "The algorithm reconstruction method according to claim 1…" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required in reply to this Office action.
Claim 10 recites the "The algorithm reconstruction method according to claim 1…" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required in reply to this Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6-9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 2005/0219251), hereinafter referred to as Chun in view of Chen et al. (US 2006/0107027), hereinafter referred to as Chen.
Referring to claim 1, Chun teaches, as claimed, a radio frequency chip, comprising a configuration interface, an interconnection bus, a processor (i.e.-system 100 comprising wireless communication system with RF spectrum, page 2, ¶16, lines 1-6; including a processor 202, bus 208, configuration module 206, see figs. 1 and 2), and at least two operation units wherein: each operation unit is provided with different operation functions (i.e.-multiple execution units configured to perform various arithmetic operations, page 2, ¶24 and page 4, ¶46, lines 1-5); the configuration interface is connected to the processor, and the configuration interface is configured to receive configuration data (i.e.-configuration module 206 stores and loads configuration information, page 3, ¶25 and page 4, ¶40, lines 1-6) and transmit the configuration data to the processor (page 4, ¶40, lines 6-9); the interconnection bus is communicated with each operation unit and is connected to the processor (page 3, ¶35, lines 5-8), and the operation unit is connected to the processor, and the operation unit configures the operation function as the target operation function according to the configuration data allocated by the processor (i.e.-the processor provides the functional operations based on downloads of configuration information, page 3, ¶35); and send allocated configuration data to each operation unit (i.e.-send configuration vectors to each execution units, page 6, ¶66).
However, Chun does not teach the configuration interface is configured to receive routing information and transmit the routing information to the processor; the routing information and the configuration data are determined according to a target operation function of the radio frequency chip; and the interconnection bus is configured to adjust an input and output relationship between each operation unit according to an instruction of the processor; and the processor is configured to send an instruction for adjusting a routing connection mode of each operation unit to the interconnection bus, and send allocated configuration data to each operation unit
On the other hand, Chen discloses a wireless communication system comprised of a processing system and reconfigurable modules connected via a communication bus (page 2, ¶17) configured to receive routing information and transmit the routing information to the processor (page 2, ¶22, 4-10); the routing information and the configuration data are determined according to a target operation function of the radio frequency chip (page 4, ¶43); and the interconnection bus is configured to adjust an input and output relationship between each operation unit according to an instruction of the processor (page 2, ¶21, lines 1-5; and ¶24, lines 12-16); and the processor is configured to send an instruction (page 2, ¶25, lines 1-5) for adjusting a routing connection mode of each operation unit to the interconnection bus, and send allocated configuration data to each operation unit (page 4, ¶44, lines 4-10).
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Chun so that the configuration interface is configured to receive routing information and transmit the routing information to the processor; the routing information and the configuration data are determined according to a target operation function of the radio frequency chip; and the interconnection bus is configured to adjust an input and output relationship between each operation unit according to an instruction of the processor; and the processor is configured to send an instruction for adjusting a routing connection mode of each operation unit to the interconnection bus, and send allocated configuration data to each operation unit, as taught by Chen. The motivation for doing so would have been to dynamically change system configuration setups/algorithms to handle variety of data processing tasks.
As to claim 2, the modified Chun teaches the radio frequency chip according to claim 1, wherein the operation unit comprises a first operation unit with arithmetic operation function (page 4, ¶45, lines 5-10) and a second operation unit with lookup table operation function (page 6, ¶66, lines 1-5).
As to claim 6, the modified Chun in view of Chen teaches the radio frequency chip according to claim 1, wherein: the interconnection bus is further communicated with each internal unit of each operation unit, and the interconnection bus is further configured to adjust the input and output relationship between each internal unit of each operation unit according to the instruction of the processor (see Chen, page 4, ¶44, 1-7); and the processor is further configured to send an instruction (see Chen, page 2, ¶25, lines 1-5) for adjusting the routing connection mode of each internal unit of each operation unit to the interconnection bus (see Chun, page 6, ¶66).
As to claim 9, the modified Chun teaches the algorithm reconstruction method according to claim 1, further comprising: adjusting, by the interconnection bus, the input and output relationship between each internal unit of each operation unit (page 6, ¶65 and see Table 2).
Referring to claims 7 and 8, the claims are substantially the same as claims 1,2 and 6, hence the rejection of claims 1,2 and 6 is applied accordingly.
Referring to claim 10, the claim is substantially the same as claim 1, hence the rejection of claim 1 is applied accordingly.
Claim Objections
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. (US 9,973,221), Furukawa (US 2007/0074001), Farwell et al. (US 6,920,545), Wretheimer et al. (US 9,436,623) and Baker et al. (US 7,170,315) do teach devices comprised of radio frequency circuitry including operation nodes/units with differing operation functions, wherein the interconnection of the nodes/units are dynamically configured to execute a desired functions.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184