DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 10, and 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Specifically, lines 7 through 10 of claim 1 recite “a highly-doped back-side layer arranged on the back side and on the plurality of edges, including on edge regions directly adjacent to a surface of the front side, a tunnel layer arranged directly on the highly-doped back-side layer, a conductive back-side layer arranged on the highly-doped back-side layer and the tunnel layer,” and the as-filed specification describes in lines 17 through 22 of page 2 “The invention is based firstly on the basic concept or insight that during a process implementation for the production of a solar cell in which the substrate is provided with a tunnel layer on the back side of the substrate and then the conductive back-side layer is applied on the tunnel layer using a doping step and a subsequent annealing step, a highly doped back-side layer is formed while these process steps are carried out, with the result that the highly doped back-side layer is arranged between the substrate and the tunnel layer.” The as-filed specification further describes in lines 8 through 11 of page 5 “Without wishing to be tied to the following hypothesis, it is assumed that the highly doped back-side layer arises during the production of the conductive back-side layer in the course of the doping and annealing steps by way of in-diffusion of the dopant through the tunnel layer into the substrate.” Additionally, the as-filed specification describes in lines 18 through 21 of page 6 “The highly doped back-side layer is preferably formed during the production of the conductive back-side layer, which is produced by means of applying, doping and annealing the back-side layer, by means of in-diffusion into the substrate. The annealing is preferably carried out at a temperature of 800 – 1100°C.”
The hypothesis presented in the as-filed specification does not enable one of ordinary skill in the art to make the highly doped back-side layer as claimed in light of the teachings of the prior art (Ha et al. (US 10,014,419) and Naber et al. (US 2020/0279970)). Specifically, Ha teaches the tunnel layer 160 may also function as a diffusion barrier for preventing the dopant of the first conductive type semiconductor region 170 from being diffused into the semiconductor substrate 100 (C8/L5-8). Naber teaches “while boron diffuses back into the polysilicon layer to a concentration equal or higher than in the substrate, the phosphorous does not migrate through the tunnel oxide to a substantial extent” ([0082]).
The teachings of both Ha and Naber do not support the hypothesis presented in the as-filed specification for the formation of the highly-doped back-side layer, and the description in the as-filed specification does not enable one skilled in the art to make and/or use the invention.
Wands Analysis: [Note MPEP 2164.01(a)]
(A) Breadth of claims:
The limitations of the claims are broad in that they merely state a “highly-doped” back-side layer without specifying a range which satisfies the limitation.
(B) The nature of the invention:
The invention is a solar cell.
(C) The state of the prior art:
Given the state of the prior art as set forth above, the formation of the claimed highly-doped back-side layer requires a more detailed disclosure by the Applicant in order to enable one skilled in the art to produce the highly-doped back-side layer in conjunction with the other structural limitations claimed.
(D) The level of one of ordinary skill:
One of ordinary skill in this art is considered to be a scientist, skilled in the methods of photovoltaic design and processes, with knowledge of standard photovoltaic devices, and familiar with parameters that affect the formation and performance of such devices.
(E) The level of predictability in the art:
The level of predictability in the art is considered to be low, inasmuch as there are numerous variables known to affect photovoltaic device manufacturing and performance.
(F) The amount of direction provided by the inventor:
The inventor does not provide adequate direction as to how to formulate a process which meets the claim limitations. The specification describes the claimed process with language that is essentially the same as that recited in the claims or entirely conventional in the art. There is not adequate guidance as to what the specific process parameters should be, beyond the description in lines 18 through 21 of page 6 of the as-filed specification which states “The highly doped back-side layer is preferably formed during the production of the conductive back-side layer, which is produced by means of applying, doping and annealing the back-side layer, by means of in-diffusion into the substrate. The annealing is preferably carried out at a temperature of 800 – 1100°C.”
(G) The existence of working examples:
There are no examples in the instant specification that provide details as to how such a process provides the claimed highly-doped back-side layer, and therefore, does not enable one of ordinary skill in the art the ability to produce the invention.
(H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure:
The Applicant has not enabled one of ordinary skill in the art at the time of the invention to produce the invention. Therefore, an undue level of experimentation would be required for one of ordinary skill in the art at the time of the invention to produce the specifics of the claimed invention.
In light of the above considerations, the Applicant has not enabled one of ordinary skill in the art to make and/or use the claimed invention.
Claims 1-3, 10, and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, line 7 of claim 1 recites “a highly-doped” back-side layer, however, the term “highly” is a relative term which renders the claim indefinite. The term “highly” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Claims 2-3, 10, and 18-20 are rejected due to their respective dependence on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 10, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 2020/0220039).
Regarding claim 1, Chang discloses a solar cell (abstract) comprising: a
substrate having a front side, a back side and a plurality of edges extending between the front side and the back side (110A in Fig. 39 has a front side (top side), a back side (bottom side), and edges between the front and back sides), a conductive front-side layer arranged on a surface of the front side (shown in annotated Fig. 39 below), a front-side electrode arranged on the front side and electrically connected to the conductive front-side layer (140A in Fig. 39), a tunnel layer arranged directly on the back side (160A in Fig. 39; [0078] – [0081]; [0078] discloses that 160 may allow a carrier generated in the substrate to pass therethrough; it is noted that a layer having the capability of tunneling satisfies the limitation “a tunnel layer”), a conductive back-side layer arranged on the tunnel layer (170A in Fig. 39 in relation to layer 160A), a back-side electrode arranged on the back side and electrically connected to the conductive back-side layer (150A in Fig. 39 in relation to 170A).
While Chang does not explicitly disclose a highly-doped back-side layer arranged on the back side and on the plurality of edges, including on edge regions directly adjacent to a surface of the front side, a tunnel layer arranged directly on the highly-doped back side layer, a conductive back-side layer arranged on the highly-doped back side layer and the tunnel layer; it is noted that both Chang and the as-filed specification describe similar processes for forming the conductive back-side layer. Specifically, Chang discloses “when the semiconductor substrate 110 contains the first conductivity type dopant and the first conductivity type dopant is doped at a higher concentration than the semiconductor substrate 110 in the first conductive region 170, the first conductive region 170 may operate as a back surface field (BSF)” ([0082]); and further discloses a thickness of the control passivation layer 160 may be formed to be 0.5 nm to 2.5 nm ([0080]); and additionally discloses a heat treatment step of 800 to 1000°C ([0152] – [0153]). The as-filed specification on lines 18 through 21 of page 6 describes “The highly doped back-side layer is preferably formed during the production of the conductive back-side layer, which is produced by means of applying, doping and annealing the back-side layer, by means of in-diffusion into the substrate. The annealing is preferably carried out at a temperature of 800 – 1100°C.”
Based on the similarity in the manner in which the conductive back-side layer is formed in both Chang and the as-filed specification, one of ordinary skill in the art at the time the invention was filed would expect the formation of a highly doped back-side layer between the substate and layer 160A of Chang. It is noted that when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Chang further discloses an insulation portion formed directly on the surface of the front side (130A in W200 in Fig. 39) and on the plurality of edges adjacent to the surface of the front side (130A in relation to the plurality of edges of 110A in Fig. 39), wherein a back-side layer assembly comprising the highly-doped back-side layer, the tunnel layer and the conductive back-side layer (depicted by D2 in Fig. 39) is absent in the insulation portion (insulation portion depicted as W200 in Fig. 39).
It is noted that with regard to the limitation “cut out,” the limitation is directed to the manner in which the apparatus is made, and it is noted that said limitations are not given patentable weight in the product claims. Even though a product-by-process is defined by the process steps by which the product is made, determination of patentability is based on the product itself and does not depend on its method of production. In re Thorpe, 777 F.2d 695, 227 USPQ 964 (Fed. Cir. 1985).
Regarding the limitation “such that electrical contact between the highly-doped back-side layer and the conductive front-side layer is structurally prevented,” when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
[AltContent: arrow][AltContent: textbox (conductive front-side layer)]
PNG
media_image1.png
315
506
media_image1.png
Greyscale
Regarding claim 2, Chang discloses all the claim limitations as set forth above. Chang further discloses the insulation portion has a width of 20 microns or greater ([0213]), and wherein the width of the insulation portion corresponds to a distance between the conductive front-side layer and the back-side layer assembly (distance between D1 and D2 in Fig. 39).
Regarding claim 3, Chang discloses all the claim limitations as set forth above. Chang further discloses a back-side passivation layer arranged on a side of the conductive back-side layer facing away from the tunnel layer (180A in Fig. 39).
Regarding claims 10 and 19, Chang discloses all the claim limitations as set forth above. Chang further discloses the conductive back-side layer is formed as an n-type emitter layer ([0081]) and the conductive front-side layer is formed as a p-type emitter layer ([0090]).
Regarding claims 18 and 20, Chang discloses all the claim limitations as set forth above. Chang further discloses the n-type emitter layer is an n-type poly-Si layer ([0081]).
Claims 1-3, 10, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2020/0220039) in view of Lenes et al. (US 2018/0277701).
Regarding claim 1, Chang discloses a solar cell (abstract) comprising: a
substrate having a front side, a back side and a plurality of edges extending between the front side and the back side (110A in Fig. 39 has a front side (top side), a back side (bottom side), and edges between the front and back sides), a conductive front-side layer arranged on a surface of the front side (shown in annotated Fig. 39 below), a front-side electrode arranged on the front side and electrically connected to the conductive front-side layer (140A in Fig. 39), a tunnel layer arranged directly on the back side (160A in Fig. 39; [0078] – [0081]; [0078] discloses that 160 may allow a carrier generated in the substrate to pass therethrough; it is noted that a layer having the capability of tunneling satisfies the limitation “a tunnel layer”), a conductive back-side layer arranged on the tunnel layer (170A in Fig. 39 in relation to layer 160A), a back-side electrode arranged on the back side and electrically connected to the conductive back-side layer (150A in Fig. 39 in relation to 170A).
Chang does not explicitly disclose a highly-doped back-side layer arranged on a surface of the back side.
Lenes discloses a solar cell (abstract) and further discloses a highly-doped back-side layer arranged on a surface of the back side of a substrate (141 in Fig. 5; [0080]; it is noted that the limitation does not specify a range for the limitation “highly-doped”).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a highly-doped back-side layer, as disclosed by Lenes, on a surface of the back side of the substrate of Chang, because as taught by Lenes, the region serves for lateral conduction of the emitter, i.e. as a spreading layer ([0079]). Additionally, Chang discloses the embodiment allows thinner doped polysilicon layers which is deemed beneficial for the through-put time ([0079]).
Modified Chang further discloses an insulation portion formed directly on the surface of the front side (Chang - 130A in W200 in Fig. 39) and on the plurality of edges adjacent to the surface of the front side (Chang - 130A in relation to the plurality of edges of 110A in Fig. 39), wherein a back-side layer assembly comprising the highly-doped back-side layer, the tunnel layer and the conductive back-side layer (Chang - depicted by D2 in Fig. 39) is absent in the insulation portion (Chang - insulation portion depicted as W200 in Fig. 39 does not contain the highly-doped back-side layer (141 in Lenes of modified Chang as set forth above) and layers 160A and 170A of Chang).
It is noted that with regard to the limitation “cut out,” the limitation is directed to the manner in which the apparatus is made, and it is noted that said limitations are not given patentable weight in the product claims. Even though a product-by-process is defined by the process steps by which the product is made, determination of patentability is based on the product itself and does not depend on its method of production. In re Thorpe, 777 F.2d 695, 227 USPQ 964 (Fed. Cir. 1985).
Regarding the limitation “such that electrical contact between the highly-doped back-side layer and the conductive front-side layer is structurally prevented,” when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Regarding claim 2, modified Chang discloses all the claim limitations as set forth above. Chang further discloses the insulation portion has a width of 20 microns or greater ([0213]), and wherein the width of the insulation portion corresponds to a distance between the conductive front-side layer and the back-side layer assembly (distance between D1 and D2 in Fig. 39).
Regarding claim 3, modified Chang discloses all the claim limitations as set forth above. Chang further discloses a back-side passivation layer arranged on a side of the conductive back-side layer facing away from the tunnel layer (180A in Fig. 39).
Regarding claims 10 and 19, modified Chang discloses all the claim limitations as set forth above. Chang further discloses the conductive back-side layer is formed as an n-type emitter layer ([0081]) and the conductive front-side layer is formed as a p-type emitter layer ([0090]).
Regarding claims 18 and 20, modified Chang discloses all the claim limitations as set forth above. Chang further discloses the n-type emitter layer is an n-type poly-Si layer ([0081]).
Response to Arguments
Applicant's arguments filed 03/17/2026 have been fully considered but they are not persuasive. Specifically, Applicant argues that one of ordinary skill would understand that Ha teaches a highly-doped layer at a back side of a TOPCon solar cell. Applicant further asserts that it is well known in the art that while such a tunnel layer affects dopant diffusion, it does not prevent dopant from being in-diffused into the substrate during manufacture of the cell. Applicant further argues that the processes are well known such that one of ordinary skill in the art would have understood how to form the recited tunnel layer, conductive-back side layer, and of course, how to form the highly doped back side layer that is the result of dopant diffusion into the silicon substrate following annealing, and that such processes are well known and described thoroughly in the prior art.
In response to Applicant’s argument, as set forth in the office action, the
hypothesis presented in the as-filed specification does not enable one of ordinary skill in the art to make the highly doped back-side layer as claimed in light of the teachings of the prior art (Ha et al. (US 10,014,419) and Naber et al. (US 2020/0279970)). Specifically, Ha teaches the tunnel layer 160 may also function as a diffusion barrier for preventing the dopant of the first conductive type semiconductor region 170 from being diffused into the semiconductor substrate 100 (C8/L5-8). Naber teaches “while boron diffuses back into the polysilicon layer to a concentration equal or higher than in the substrate, the phosphorous does not migrate through the tunnel oxide to a substantial extent” ([0082]).
The teachings of both Ha and Naber do not support the hypothesis presented in the as-filed specification for the formation of the highly-doped back-side layer, and the description in the as-filed specification does not enable one skilled in the art to make and/or use the invention. (Additionally, see Wands Analysis set forth in the office action).
Applicant has not provided evidence supporting the assertion that processes which form the highly doped back side layer are well known and described thoroughly in the prior art.
Applicant argues that Ha describes a highly doped region (a “region which has a higher doping concentration than the semiconductor substrate 100) in the substrate is formed. In response to Applicant’s argument, Ha does not disclose a highly-doped layer, and the disclosure of Ha does not support the assumption of the as-filed specification that the highly doped back-side layer arises during the production of the conductive back-side layer in the course of the doping and annealing steps by way of in-diffusion of the dopant through the tunnel layer into the substrate (see lines 8 through 11 of page 5 of the as-filed specification, as set forth in the 112(a) rejection above).
Applicant argues the term “highly doped” is well understood by those of ordinary skill in the art, and as such, does not require an explicit definition in the specification. In response to Applicant’s argument, the dopant concentration required to satisfy the limitation “highly doped” is unclear based on the current record. For example, highly doped is described as a higher doping concentration than the semiconductor substrate, and also described as dopant concentrations exceeding 1018 atoms per cubic centimeter (page 11 of Applicant’s 03/17/2026 Remarks). It is unclear as to whether highly doped refers to a dopant concentration which is simply higher than that of a substrate, or whether highly doped refers to a dopant concentration exceeding 1018 atoms per cubic centimeter. The dopant concentration required to satisfy the claim limitation “highly doped” is not defined. As set forth in the office action, the term “highly” is a relative term which renders the claim indefinite. The term “highly” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Applicant argues that the office action relies on impermissible hindsight, and that one of ordinary skill would understand that Chang does not teach a highly-doped back side layer. In response to Applicant’s argument, as set forth in the office action, while Chang does not explicitly disclose a highly-doped back-side layer arranged on the back side and on the plurality of edges, including on edge regions directly adjacent to a surface of the front side, a tunnel layer arranged directly on the highly-doped back side layer, a conductive back-side layer arranged on the highly-doped back side layer and the tunnel layer; it is noted that both Chang and the as-filed specification describe similar processes for forming the conductive back-side layer. Specifically, Chang discloses “when the semiconductor substrate 110 contains the first conductivity type dopant and the first conductivity type dopant is doped at a higher concentration than the semiconductor substrate 110 in the first conductive region 170, the first conductive region 170 may operate as a back surface field (BSF)” ([0082]); and further discloses a thickness of the control passivation layer 160 may be formed to be 0.5 nm to 2.5 nm ([0080]); and additionally discloses a heat treatment step of 800 to 1000°C ([0152] – [0153]). The as-filed specification on lines 18 through 21 of page 6 describes “The highly doped back-side layer is preferably formed during the production of the conductive back-side layer, which is produced by means of applying, doping and annealing the back-side layer, by means of in-diffusion into the substrate. The annealing is preferably carried out at a temperature of 800 – 1100°C.”
Based on the similarity in the manner in which the conductive back-side layer is formed in both Chang and the as-filed specification, one of ordinary skill in the art at the time the invention was filed would expect the formation of a highly doped back-side layer between the substate and layer 160A of Chang. It is noted that when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Applicant argues that Chang describes region 120 is formed by diffusing the second conductivity type dopant into the front surface of the substrate, and that one would expect the same explicit description if Chang contemplated the formation of a highly-doped back side layer. In response of Applicant’s argument, notwithstanding the lack of an explicit disclosure in Chang, as set forth above, based on the similarity in the manner in which the conductive back-side layer is formed in both Chang and the as-filed specification, one of ordinary skill in the art at the time the invention was filed would expect the formation of a highly doped back-side layer between the substate and layer 160A of Chang. It is noted that when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
It is noted that with regard to Applicant’s remaining arguments with respect to claims 1-3, 10, and 18-20, the arguments have been considered but are moot because the new ground of rejection does not rely on the embodiment in Chang (embodiment of Fig. 3) applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMIR AYAD whose telephone number is (313) 446-6651. The examiner can normally be reached Monday - Friday, 8:30am - 5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Barton can be reached at (571) 272-1307. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/TAMIR AYAD/Primary Examiner, Art Unit 1726
Prosecution Insights