DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant’s amendments filed on 5/10/2024 have been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 19-24 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Perzlmaier et al (US 2018/0062027).
Regarding Claim 19, Perzlmaier et al discloses an optoelectronic component (optoelectronic semiconductor components LED [0030] Fig 1A-E) comprising:
a structured region (mesa structures 3 [0084] Fig 1A-E) comprising:
a semiconductor body (semiconductor layer sequence 2 [0083] Fig 1A-E) comprising a first semiconductor region (n-conductive region 21 [0083] Fig 1A-E) and a second semiconductor region (p-conductive region 23 [0083] Fig 1A-E), which have different conductivities (n-type and p-type [0083]);
a first main surface (mesa tops 31 [0084] Fig 1A-E) and a second main surface (mesa bottom of layer 2 Fig 1A-E); and
at least one first delimiting surface (shown in annotated Fig 1A-E) and at least one second delimiting surface (shown in annotated Fig 1A-E), wherein the at least one first delimiting surface (shown in annotated Fig 1A-E) laterally delimits a recess (shown in annotated Fig 1A-E) extending from the first main surface (mesa tops 31 [0084] Fig 1A-E) into the structured region (3 Fig 1A-E), and the at least one second delimiting surface (shown in annotated Fig 1A-E) delimits the recess (shown in annotated Fig 1A-E) on a side facing the second main surface (mesa bottom of layer 2 Fig 1A-E); and
an electrically weakly conductive or non-conductive protective layer (flank coating 6 [0087] Fig 1A-E), which is arranged on the at least one first delimiting surface (shown in annotated Fig 1A-E) and covers a junction (active zone 22 [0084] Fig 1A-E)) between the first semiconductor region (21 Fig 1A-E) and the second semiconductor region (23 Fig 1A-E) in the recess (shown in annotated Fig 1A-E),
wherein the first main surface (mesa tops 31 [0084] Fig 1A-E) is not covered by the protective layer (flank coating 6 [0087] Fig 1A-E) and the protective layer (flank coating 6 [0087] Fig 1A-E) does not adjoin any further protective layer (flank coating 6 [0087] Fig 1A-E) on a side facing the junction (22 Fig 1A-E) and on a side facing away from the junction (22 Fig 1A-E), and
wherein the protective layer (6 Fig 1A-E) is retracted from the first delimiting surface (shown in annotated Fig 1A-E) and the second delimiting surface (shown in annotated Fig 1A-E) and has a vertical distance, which is greater than zero, from the first delimiting surface (shown in annotated Fig 1A-E) and the second delimiting surface (shown in annotated Fig 1A-E), or wherein the protective layer (6 Fig 1A-E) has an L-shape (layer 6 has sublayers 61 and 62 wherein sublayer 61 has an L-shape in the cross-section shown in Fig 2A-C) in cross-section.
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Regarding Claim 20, Perzlmaier et al discloses the limitations of claim 19 as explained above. Perzlmaier et al further discloses
wherein the protective layer (flank coating 6 [0087] Fig 1A-E) is a layer conformally deposited (shown in Fig 1C) on the structured region (mesa structures 3 [0084] Fig 1A-E).
Regarding Claim 21, Perzlmaier et al discloses the limitations of claim 19 as explained above. Perzlmaier et al further discloses
wherein the protective layer (flank coating 6 Fig 1A-E) contains an oxide (may comprise aluminum oxide [0076]-[0077]) or nitride.
Regarding Claim 22, Perzlmaier et al discloses the limitations of claim 19 as explained above. Perzlmaier et al further discloses
wherein the protective layer (6 Fig 1A-E) is retracted (retracted horizontally toward the opening) from the first main surface (shown above in annotated Fig 1A-E) and has a vertical distance (shown above in annotated Fig 1-E), which is greater than or equal to zero, from a plane of the first main surface (shown above in annotated Fig 1A-E).
Regarding Claim 23, Perzlmaier et al discloses the limitations of claim 19 as explained above. Perzlmaier et al further discloses
wherein the protective layer (6 Fig 1A-E) extends from the first delimiting surface (shown above in annotated Fig 1A-E) to or onto the second delimiting surface (shown above in annotated Fig 1A-E) and has a vertical distance therefrom which is equal to zero.
Regarding Claim 24, Perzlmaier et al discloses the limitations of claim 19 as explained above. Perzlmaier et al further discloses
wherein the protective layer (6 Fig 1A-E) has an opening region (shown in Fig 1A-E) at the second delimiting surface (shown above in annotated Fig 1A-E), in which the second delimiting surface (shown above in annotated Fig 1A-E) is uncovered by the protective layer (6 Fig 1A-E).
Regarding Claim 27, Perzlmaier et al discloses the limitations of claim 19 as explained above. Perzlmaier et al further discloses
wherein the second delimiting surface (shown above in annotated Fig 1A-E) is formed by a surface of the second semiconductor region (23 Fig 1A-E).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 25-26 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Perzlmaier et al (US 2018/0062027) in view of Kim et al (US 2018/0019380).
Regarding Claim 25, Perzlmaier et al discloses the limitations of claim 24 as explained above. Perzlemaier et al does not directly disclose
further comprising a first electrical contact means arranged in the opening region of the protective layer.
Kim et al, in the related art of semiconductor devices that include light emitting devices, discloses
further comprising a first electrical contact (contact area 22C [0023] Fig 2/contact electrode 51 [0030] Fig 2) means arranged in the opening region (opening O1 [0029] Fig 2) of the protective layer (insulating spacer 44 [0029] Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Perzlemaier et al to include further comprising a first electrical contact means arranged in the opening region of the protective layer in order to further optimize electrical functioning of the light emitting region of the device. Further, a person of ordinary skill in the art would have recognized that having a conductive contact electrode in the opening of the device would further optimize the electrical and optical functioning in that there would be more electricity flowing through the opening region of the device (see MPEP 2143.I(D)).
Regarding Claim 26, the combination of Perzlmaier et al and Kim et al discloses the limitations of claim 25 as explained above. The combination of Perzlemaier et al and Kim et al, as applied to claim 25, does not directly disclose
further comprising a second electrical contact means arranged at the first main surface.
However, Kim et al, in the related art of semiconductor devices that include light emitting devices, discloses
further comprising a second electrical contact (first bonding metal 59 [0032] Fig 2) means arranged at the first main surface (mesa tops shown in Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Perzlmaier et al and Kim et al, as applied to claim 25, to include further comprising a second electrical contact means arranged at the first main surface in order to further optimize electrical functioning of the light emitting region of the device. Further, a person of ordinary skill in the art would have recognized that having a conductive contact electrode in the opening of the device would further optimize the electrical and optical functioning in that there would be more electricity flowing through the opening region of the device (see MPEP 2143.I(D)).
Regarding Claim 35, Perzlmaier et al discloses an optoelectronic component (optoelectronic semiconductor components LED [0030] Fig 1A-E) comprising:
a structured region (mesa structures 3 [0084] Fig 1A-E) comprising:
a semiconductor body (semiconductor layer sequence 2 [0083] Fig 1A-E) comprising a first semiconductor region (n-conductive region 21 [0083] Fig 1A-E) and a second semiconductor region (p-conductive region 23 [0083] Fig 1A-E), which have different conductivities (n-type and p-type [0083]);
a first main surface (mesa tops 31 [0084] Fig 1A-E) and a second main surface (mesa bottom of layer 2 Fig 1A-E); and
at least one first delimiting surface (shown in annotated Fig 1A-E) and at least one second delimiting surface (shown in annotated Fig 1A-E), wherein the at least one first delimiting surface (shown in annotated Fig 1A-E) laterally delimits a recess (shown in annotated Fig 1A-E) extending from the first main surface (mesa tops 31 [0084] Fig 1A-E) into the structured region (3 Fig 1A-E), and the at least one second delimiting surface (shown in annotated Fig 1A-E) delimits the recess (shown in annotated Fig 1A-E) on a side facing the second main surface (mesa bottom of layer 2 Fig 1A-E); and
an electrically weakly conductive or non-conductive protective layer (flank coating 6 [0087] Fig 1A-E), which is arranged on the at least one first delimiting surface (shown in annotated Fig 1A-E) and covers a junction (active zone 22 [0084] Fig 1A-E)) between the first semiconductor region (21 Fig 1A-E) and the second semiconductor region (23 Fig 1A-E) in the recess (shown in annotated Fig 1A-E),
wherein the first main surface (mesa tops 31 [0084] Fig 1A-E) is not covered by the protective layer (flank coating 6 [0087] Fig 1A-E).
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Perzlmaier et al does not disclose
wherein a further protective layer, which is arranged on the protective layer, has a greater thickness than the protective layer arranged underneath and has a convexly curved surface on a side facing away from the structured region.
Kim et al, in the related art of semiconductor devices that include light emitting devices, discloses
wherein a further protective layer (top portion of insulating spacer 44 and protective insulating layer 42 [0025] Fig 3), which is arranged on the protective layer (lower portion of insulating spacer 44 [0025] Fig 3), has a greater thickness (shown in annotated Fig 3) than the protective layer (lower portion of insulating spacer 44 Fig 3) arranged underneath and has a convexly curved surface (shown in annotated Fig 3) on a side facing away from the structured region (shown in annotated Fig 3).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Perzlmaier et al to include wherein a further protective layer, which is arranged on the protective layer, has a greater thickness than the protective layer arranged underneath and has a convexly curved surface on a side facing away from the structured region as taught by Kim et al in order to protect the semiconductor layers below when light enters the recess. Additionally, it would have been an obvious matter of design choice to optimize the thickness and/or shape of the further protective layer since such a modification would have involved a mere change in size/shape of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). A change in shape is generally recognized as being within the level of ordinary skill in the art In Re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) MPEP 2144.04.IV(B). Further, a person of ordinary skill in the art would have recognized that protecting the semiconductor layers from heat would help improve the durability and reliability of the device while also improving optical functionality (see MPEP 2143.I(D)).
Allowable Subject Matter
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 28: The prior art does not anticipate or render obvious, alone or in combination, that
Regarding Claim 28, Perzlmaier et al (US 2018/0062027) discloses
the method comprising: providing the structured region (mesa structures 3 [0084] Fig 1A-E);
generating a first initial layer (cladding 4 [0086] Fig 1C) for producing the electrically weakly conductive or non-conductive protective layer (flank coating 6 [0087] Fig 1A-E) on the first main surface (mesa tops 31 [0084] Fig 1A-E),
providing the first delimiting surface (shown in annotated Fig 1A-E) and the second delimiting surface (shown in annotated Fig 1A-E);
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Kim et al (US 2018/0019380) discloses
generating a second initial layer (second insulating layer 42’ and third insulating layer 44’) for producing a further protective layer (top portion of insulating spacer 44 and protective insulating layer 42 [0025] Fig 3), which is arranged on the protective layer (lower portion of insulating spacer 44 [0025] Fig 3), has a greater thickness (shown in annotated Fig 3) than the protective layer (lower portion of insulating spacer 44 Fig 3) arranged underneath and has a convexly curved surface (shown in annotated Fig 3) on a side facing away from the structured region (shown in annotated Fig 3).
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The reason for the indication of allowability of Claim 28 is the inclusion of
producing a structured second initial layer, wherein regions of the second initial layer which are arranged on the first main surface and regions, which are arranged on the second delimiting surface are removed; and
structuring the first initial layer by the structured second initial layer, wherein regions which are uncovered by the structured second initial layer are removed.
Specifically, the way that the reference Kim et al uses two layers as the second initial layer does not meet these claim limitations and the final resulting layer does not have the structured areas or portions where the second initial layer are removed such as the protective layer 6 shown in Fig 2 of the instant application. Further, should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references to modify the combination of Perzlmaier et al and Kim et al to meet these limitations as claimed.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 29-34 would be allowable based on their dependency on Claim 28.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dupre et al (US 2021/0126157) which discloses a method of manufacturing LEDs [0001], and Coffy et al (US 2021/0066271) which discloses light emitting electronic integrated circuit chips with delimiting surfaces which delimits chambers [0003].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812