DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 14, 25; 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youn et al. WO 2021/201844 A1 in view of Zhang et al. WO 2021/000220 A1.
Re: claims 1 and 14 (which are rejected under the same rationale), Youn teaches
1. An apparatus for display processing, comprising: a memory; and at least one processor coupled to the memory and configured to:... (“The frame generation subsystem 102 operates to generate a sequence of video frames... for display and includes a system memory 108 storing one or more software applications 110 and a set of one or more processors, such as one or more central processing units (CPUs) 112, one or more graphics processing units (GPUs) 114, and one or more display processing units (DPUs) 116.”; Youn, p. 6, line 27-p. 7, line 4)
Fig. 1 illustrates a frame generation subsystem 102 (apparatus for display processing) that includes a system memory 108 (a memory) and processors such as CPU, 112, GPU 114 and DPU 116 (at least one processor coupled to the memory).
... obtain a fence for the one or more frame content buffers, the fence for the one or more frame content buffers corresponding to the frame content buffer being rendered; (“For example, a specified signal may be provided (e.g., by a frame generation subsystem) to signal completion of rendering of a frame, such as through transmission of a data packet.”; Youn, p. 2, lines 18-20)
A specified signal (obtain a fence) is provided, to signal completion of rendering for the frame (for the one or more frame content buffers, the fence for the one or more frame content buffers corresponding to the frame content buffer being rendered).
receive a signal for the fence for the one or more frame content buffers, the signal for the fence for the one or more frame content buffers corresponding to a frame associated with the fence being finished rendering; (“For example, a specified signal may be provided (e.g., by a frame generation subsystem) to signal completion of rendering of a frame, such as through transmission of a data packet... ... a specified signal is provided by the frame generation subsystem 102 to signal completion of rendering of a frame, such as through transmission of a 2C data packet.”; Youn, p. 2, lines 18-20, ... a specified signal is provided by the frame generation subsystem 102 to signal completion of rendering of a frame, such as through transmission of a 2C data packet.)
A specified signal is provided (receive a signal for the fence for the one or more frame content buffers) to signal completion of rendering of a frame (the signal for the fence for the one or more frame content buffers corresponding to a frame associated with the fence being finished rendering).
and transfer, to a display memory of a display, data for the first frame associated with a first synchronization signal at a default transfer rate or a boosted transfer rate based on whether the data for the first frame is ready for the transfer prior to or at the first synchronization signal. (“In the absence of an indication of a late/delayed rendering for the current frame being rendered (e.g., in response to determining that the current frame has finished rendering by a certain time or threshold associated with the target frame rate), then at block 218 the timing controller 122 utilizes a default discrete VRR mode for the upcoming display frame period. When the timing controller 122 is in the default discrete VRR mode, the most-recently-rendered frame is selected for block 208 as the next image to be displayed and the frame rate for the rendered frame is set to the selected target frame rate for block 212, and thus the frame period for displaying the rendered frame is set to the target frame period corresponding to the target frame rate.”; Youn, p. 12, lines 14-23)
In response to determining that the current frame has finished rendering (data for the first frame is ready for the transfer) (transfer, to a display memory, data for the first frame associated with a first synchronization signal) by a certain time or threshold associated with the target frame rate (prior to or at the first synchronization signal), a default VRR mode is used. In default VRR mode, the previous frame is selected as the next image to be displayed and the frame rate for the rendered frame is set to the selected target frame rate (default transfer rate), thus setting the frame period to the target frame period corresponding to the target frame rate.
(“... if the timing controller 122 instead detects delayed rendering for the current frame, then... the discrete VRR scheme 144 selects one of two compensatory discrete VRR modes to compensate for the delayed rendering... These two modes include a frame stretch mode and a frame insertion mode.... in response to detecting a delayed rendering, at block 220 the timing controller determines whether the current frame rate is set to the maximum frame rate... If not, then the timing controller 122 utilizes the frame insertion mode at block 222 to control the timing and display of the upcoming display frame period. As an overview, when in the frame insertion mode, the most-recently-displayed frame (that is, the “previous” frame) is selected again at block 208 as the next frame to be displayed and for the repeated display of this previous frame at block 212, a faster frame rate... is selected so that the corresponding display frame period for the again-displayed previous frame is shortened compared to the nominal target frame period... and then the rendering-delayed frame is selected for display... for the following display frame period, and displayed at the target frame rate... ”; Youn, p. 12, line 30-p. 13, line 3, p. 13, line 21-p. 14, line 2, Fig. 2)
In response to detecting delayed rendering for the current frame, the discrete VRR scheme selects, for example, a frame insertion mode to compensate for delayed rendering. In the frame insertion mode, the previously displayed frame is selected (transfer, to a display memory, data for the first frame associated with a first synchronization signal) as the next frame to be displayed, which results in a faster frame rate (boosted transfer rate based on whether the data for the first frame is ready for the transfer prior to the first synchronization signal) thus shortening the display frame period.
Youn is silent regarding obtain one or more frame content buffers for a frame composition cycle;... compose, based on the signal for the fence for the one or more frame content buffers, a first frame associated with the one or more frame content buffers for the frame composition cycle, however Zhang teaches
... obtain one or more frame content buffers for a frame composition cycle;... (“... a frame compose or SF mechanism can consume the frame or help send the frame to the buffer queue or display.”; Zhang, [0043])
A frame compose can consume the frame or send the frame to the buffer queue (obtain one or more frame content buffers for a frame composition cycle).
... compose, based on the signal for the fence for the one or more frame content buffers, a first frame associated with the one or more frame content buffers for the frame composition cycle; (“As shown in Fig. 3, when the buffer is ready, the frame composer or SF mechanism can be triggered directly. Additionally, a jank can be eliminated if a fence of a kernel graphics support layer (KGSL) is signaled before the TE arrives.”; Zhang, [0045], Fig. 3)
A fence signals that the buffer (frame content buffer) is ready before the TE signal arrives, the frame composer is triggered (compose, based on the signal for the fence the one or more frame content buffers) to compose a frame (a first frame associated with the one or more frame content buffers for the frame composition cycle). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Youn by adding the feature of obtain one or more frame content buffers for a frame composition cycle;... compose, based on the signal for the fence for the one or more frame content buffers, a first frame associated with the one or more frame content buffers for the frame composition cycle, in order to reduce janks and increase FPS, as taught by Zhang ([0037]).
Claim 25 is a medium analogous to the apparatus of claim 1, is similar in scope and is rejected under the same rationale. Re: claim 25, Youn and Zhang teach
25. A non-transitory computer-readable medium storing computer executable code, the code when executed by at least one processor, causes the at least one processor to: (“The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storable medium. The software can include the instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques describe above.”; Youn, p. 25, lines 11-15)
A non-transitory computer-readable storage medium stores instructions that is executed by one or more processors.
Re: claims 2 and 15 (which are rejected under the same rationale), Youn and Zhang teach
2. The apparatus of claim 1, wherein if the data for the first frame is ready for the transfer prior to or at the first synchronization signal, the data for the first frame is transferred at the default transfer rate. (“In the absence of an indication of a late/delayed rendering for the current frame being rendered (e.g., in response to determining that the current frame has finished rendering by a certain time or threshold associated with the target frame rate), then at block 218 the timing controller 122 utilizes a default discrete VRR mode for the upcoming display frame period. When the timing controller 122 is in the default discrete VRR mode, the most-recently-rendered frame is selected for block 208 as the next image to be displayed and the frame rate for the rendered frame is set to the selected target frame rate for block 212, and thus the frame period for displaying the rendered frame is set to the target frame period corresponding to the target frame rate.”; Youn, p. 12, lines 14-23)
In response to determining that the current frame has finished rendering (if the data of the first frame is ready for transfer) by a certain time or threshold associated with the target frame rate (prior to or at the first synchronization signal), then a default discrete VRR mode is used for the upcoming display frame period. In the default discrete VRR mode, the previous frame is selected as the next image to be displayed (the data for the first frame is transferred) and the frame rate for the rendered frame is set to the selected target frame rate (the data is transferred at the default transfer rate).
(“Timing row 506 represents the state of the TE signal 136, whereby in this example an active-hi pulse in the TE signal 136 signals the frame generation subsystem 102 to begin transferring the next rendered frame to the GRAM 118. Timing row 508 represents the state of a vertical blank (VSYNC) signal generated and used ty the timing controller 122 to control the scan out of a frame from the GRAM 118 to the display panel 106 for display, and thus the VSYNC signal represents the timing of each frame period. For this example, the VSYNC signal is synchronized to the active-high pulses in the TE signal 136, whereby the VSYNC signal is pulsed active-low in response to a corresponding pulse in the TE signal 136, and this pulse in the VSYNC signal initiates commencement of the frame period for the corresponding frame being scanned out and displayed at the display panel 106. Timing row 510 represents the scan out of a frame on a row-by-row basis for a corresponding frame period (represented in the VSYNC signal).”; Youn, p. 17, lines 19-32, Fig. 5)
Fig. 5 illustrates a timing diagram, where timing row 506 represents the TE signal for transferring the next rendered frame to the GRAM and timing row 508 represents the Vsync signal that represents timing of each frame period. The Vsync signal is synchronized to the TE signal, where the Vsync signal is initiates commencement of the frame period for the corresponding frame being scanned out and displayed. Thus, in this case the frame is transferred at the first synchronization signal (Vsync).
Re: claims 3 and 16 (which are rejected under the same rationale), Youn and Zhang teach
3. The apparatus of claim 2, wherein the data for the first frame being ready for the transfer prior to or at the first synchronization signal corresponds to the reception of the signal for the fence for the one or more frame content buffers being on-time. (“In the absence of an indication of a late/delayed rendering for the current frame being rendered (e.g., in response to determining that the current frame has finished rendering by a certain time or threshold associated with the target frame rate), then at block 218 the timing controller 122 utilizes a default discrete VRR mode for the upcoming display frame period. When the timing controller 122 is in the default discrete VRR mode, the most-recently-rendered frame is selected for block208 as the next image to be displayed and the frame rate for the rendered frame is set to the selected target frame rate for block 212, and thus the frame period for displaying the rendered frame is set to the target frame period corresponding to the target frame rate.”; Youn, p. 12, lines 14-23)
In response to determining that the current frame has finished rendering (the first frame being ready for the transfer prior to or at the first synchronization signal) by a certain time or threshold associated with the target frame rate (reception of the signal for the fence for the one or more frame content buffers being on time).
(“Timing row 506 represents the state of the TE signal 136, whereby in this example an active-hi pulse in the TE signal 136 signals the frame generation subsystem 102 to begin transferring the next rendered frame to the GRAM 118. Timing row 508 represents the state of a vertical blank (VSYNC) signal generated and used ty the timing controller 122 to control the scan out of a frame from the GRAM 118 to the display panel 106 for display, and thus the VSYNC signal represents the timing of each frame period. For this example, the VSYNC signal is synchronized to the active-high pulses in the TE signal 136, whereby the VSYNC signal is pulsed active-low in response to a corresponding pulse in the TE signal 136, and this pulse in the VSYNC signal initiates commencement of the frame period for the corresponding frame being scanned out and displayed at the display panel 106. Timing row 510 represents the scan out of a frame on a row-by-row basis for a corresponding frame period (represented in the VSYNC signal).”; Youn, p. 17, lines 19-32, Fig. 5)
Fig. 5 illustrates a timing diagram, where timing row 506 represents the TE signal for transferring the next rendered frame to the GRAM and timing row 508 represents the Vsync signal that represents timing of each frame period. The Vsync signal is synchronized to the TE signal, where the Vsync signal is initiates commencement of the frame period for the corresponding frame being scanned out and displayed. Thus, in this case the frame is transferred at the first synchronization signal (Vsync).
Re: claims 4 and 17 (which are rejected under the same rationale), Youn and Zhang teach
4. The apparatus of claim 3, wherein the on-time reception of the signal for the fence for the one or more frame content buffers is associated with a rendering time at a graphics processing unit (GPU) that is less than or equal to a rendering time threshold. (“In the absence of an indication of a late/delayed rendering for the current frame being rendered (e.g., in response to determining that the current frame has finished rendering by a certain time or threshold associated with the target frame rate), then at block 218 the timing controller 122 utilizes a default discrete VRR mode for the upcoming display frame period. When the timing controller 122 is in the default discrete VRR mode, the most-recently-rendered frame is selected for block 208 as the next image to be displayed and the frame rate for the rendered frame is set to the selected target frame rate for block 212, and thus the frame period for displaying the rendered frame is set to the target frame period corresponding to the target frame rate.”; Youn, p. 12, lines 14-23)
In response to determining that the current frame has finished rendering by a certain time or threshold associated with the target frame rate (the on-time reception of the signal for the fence for the one or more content buffers), the previous frame is selected as the next frame to be displayed, the frame rate is set to the target frame rate and the frame period for displaying the rendered frame is set to the target frame period (associated with a rendering time at a graphics processing unit that is less than or equal to a rendering time threshold) corresponding to the target frame rate.
Re: claims 5 and 18 (which are rejected under the same rationale), Youn and Zhang teach
5. The apparatus of claim 1, wherein if the data for the first frame is not ready for the transfer prior to or at the first synchronization signal, the data for the first frame is transferred at the boosted transfer rate. (“... if the timing controller 122 instead detects delayed rendering for the current frame, then... the discrete VRR scheme 144 selects one of two compensatory discrete VRR modes to compensate for the delayed rendering... These two modes include a frame stretch mode and a frame insertion mode... in response to detecting a delayed rendering, at block 220 the timing controller determines whether the current frame rate is set to the maximum frame rate... If not, then the timing controller 122 utilizes the frame insertion mode at block 222 to control the timing and display of the upcoming display frame period. As an overview, when in the frame insertion mode, the most-recently-displayed frame (that is, the “previous” frame) is selected again at block 208 as the next frame to be displayed and for the repeated display of this previous frame at block 212, a faster frame rate... is selected so that the corresponding display frame period for the again-displayed previous frame is shortened compared to the nominal target frame period... and then the rendering-delayed frame is selected for display... for the following display frame period, and displayed at the target frame rate...”; Youn, p. 12, line 30-p. 13, line 3, 13, line 21-p. 14, line 2, Fig. 2)
In response to detecting delayed rendering (if the data for the first frame is not ready for the transfer prior to or at the first synchronization signal), frame insertion mode is used. In frame insertion mode, the previous frame is selected (the data for the first frame is transferred) as the next frame to be displayed, which results in a faster frame rate (boosted transfer rate).
Re: claims 6 and 19 (which are rejected under the same rationale), Youn and Zhang teach
6. The apparatus of claim 5, wherein the data for the first frame not being ready for the transfer prior to or at the first synchronization signal corresponds to the reception of the signal for the fence for the one or more frame content buffers being delayed. (“With a timing controller 122 so initialized, at block 216 of the frame selection process 204 the timing controller 122 monitors the frame rendering process of block 206 for an indication that rendering of the current frame is, or will be, “delayed”; that may or will not be ready for scan out to the display panel 106... when the frame period for the previous frame (that is, the frame that is currently being displayed) ends and the frame period for the next frame to be displayed begins.)”; Youn, p. 12, lines 1-7)
The timing controller monitors the frame rendering process for an indication (reception of the signal for the fence for the one or more frame content buffers being delayed) that rendering of the current frame is delayed (the data for the first frame not being ready for transfer prior to or at the first synchronization signal).
Re: claims 7 and 20 (which are rejected under the same rationale), Youn and Zhang teach
7. The apparatus of claim 6, wherein the delayed reception of the signal for the fence for the one or more frame content buffers is associated with a rendering time at a graphics processing unit (GPU) that is greater than a rendering time threshold. (“With a timing controller 122 so initialized, at block 216 of the frame selection process 204 the timing controller 122 monitors the frame rendering process of block 206 for an indication that rendering of the current frame is, or will be, “delayed”; that may or will not be ready for scan out to the display panel 106... when the frame period for the previous frame (that is, the frame that is currently being displayed) ends and the frame period for the next frame to be displayed begins.)”; Youn, p. 12, lines 1-7)
The timing controller monitors the frame rendering process for an indication (the delayed reception of the signal for the fence for the one or more frame content buffers) that rendering of the current frame is delayed and will not be ready for scan out to the display panel when the frame period (associated with a rendering time at a graphics processing unit (GPU that is greater than a rendering time threshold) for the previous frame ends.
Re: claims 8 and 21 (which are rejected under the same rationale), Youn and Zhang teach
8. The apparatus of claim 1, wherein the default transfer rate is associated with a first clock frequency at a display processing unit (DPU), and the boosted transfer rate is associated with a second clock frequency at the DPU, the second clock frequency being higher than the first clock frequency. (“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136... as well as a vertical blank (VSYNC) signal and a scan start signal... The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118...”; Youn, p. 7, line 30-p. 8, line 2, Fig. 1)
The timing controller uses clock signals (first clock frequency) to generate various control signals including a TE signal, which initiates the transfer of the next frame.
(“In the absence of an indication of a late/delayed rendering for the current frame being rendered (e.g., in response to determining that the current frame has finished rendering by a certain time or threshold associated with the target frame rate), then at block 218 the timing controller 122 utilizes a default discrete VRR mode for the upcoming display frame period. When the timing controller 122 is in the default discrete VRR mode, the most-recently-rendered frame is selected for block 208 as the next image to be displayed and the frame rate for the rendered frame is set to the selected target frame rate for block 212, and thus the frame period for displaying the rendered frame is set to the target frame period corresponding to the target frame rate.”; Youn, p. 12, lines 14-23)
In response to determining that the current frame has finished rendering (if the data of the first frame is ready for transfer) by a certain time or threshold associated with the target frame rate, then a default discrete VRR mode is used for the upcoming display frame period. In the default discrete VRR mode, the previous frame is selected as the next image to be displayed and the frame rate for the rendered frame is set to the selected target frame rate (the default transfer rate is associated with a first clock frequence at a display processing unit).
(“... if the timing controller 122 instead detects delayed rendering for the current frame, then... the discrete VRR scheme 144 selects one of two compensatory discrete VRR modes to compensate for the delayed rendering... These two modes include a frame stretch mode and a frame insertion mode.... in response to detecting a delayed rendering, at block 220 the timing controller determines whether the current frame rate is set to the maximum frame rate... If not, then the timing controller 122 utilizes the frame insertion mode at block 222 to control the timing and display of the upcoming display frame period. As an overview, when in the frame insertion mode, the most-recently-displayed frame (that is, the “previous” frame) is selected again at block 208 as the next frame to be displayed and for the repeated display of this previous frame at block 212, a faster frame rate... is selected so that the corresponding display frame period for the again-displayed previous frame is shortened compared to the nominal target frame period... and then the rendering-delayed frame is selected for display... for the following display frame period, and displayed at the target frame rate... ”; Youn, p. 12, line 30-p. 13, line 3, p. 13, line 21-p. 14, line 2, Fig. 2)
In response to detecting delayed rendering for the current frame, the discrete VRR scheme selects, for example, a frame insertion mode to compensate for delayed rendering. In the frame insertion mode, the previously displayed frame is selected as the next frame to be displayed, which results in a faster frame rate (the boosted transfer rate is associated with the second clock frequency at the DPU, the second clock frequency being higher than the first clock frequency), thus shortening the display frame period.
Re: claims 9 and 22 (which are rejected under the same rationale), Youn and Zhang teach
9. The apparatus of claim 1, wherein the first synchronization signal precedes a corresponding tear effect (TE) signal associated with the display by a predetermined offset. (“Timing row 506 represents the state of the TE signal 136, whereby in this example an active-hi pulse in the TE signal 136 signals the frame generation subsystem 102 to begin transferring the next rendered frame to the GRAM 118. Timing row 508 represents the state of a vertical blank (VSYNC) signal generated and used ty the timing controller 122 to control the scan out of a frame from the GRAM 118 to the display panel 106 for display, and thus the VSYNC signal represents the timing of each frame period. For this example, the VSYNC signal is synchronized to the active-high pulses in the TE signal 136, whereby the VSYNC signal is pulsed active-low in response to a corresponding pulse in the TE signal 136, and this pulse in the VSYNC signal initiates commencement of the frame period for the corresponding frame being scanned out and displayed at the display panel 106. Timing row 510 represents the scan out of a frame on a row-by-row basis for a corresponding frame period (represented in the VSYNC signal).”; Youn, p. 17, lines 19-32, Fig. 5)
Fig. 5 illustrates a timing diagram, where timing row 506 represents the TE signal for transferring the next rendered frame to the GRAM and timing row 508 represents the Vsync signal that represents timing of each frame period. The Vsync signal (first synchronization signal) is synchronized to the TE signal (first synchronization signal precedes a corresponding TE signal associated with the display by a predetermined offset), where the Vsync signal is initiates commencement of the frame period for the corresponding frame being scanned out and displayed.
Re: claims 10 and 23 (which are rejected under the same rationale), Youn and Zhang teach
10. The apparatus of claim 9, wherein the transfer of the data for the first frame is started before or at the corresponding TE signal. (“Timing row 506 represents the state of the TE signal 136, whereby in this example an active-hi pulse in the TE signal 136 signals the frame generation subsystem 102 to begin transferring the next rendered frame to the GRAM 118.”; Youn, p. 17, lines 19-22, Fig. 5)
Fig. 5 illustrates a timing diagram, where timing row 506 represents the TE signal which signals the frame generation subsection to begin transferring the next rendered frame to the GRAM (the transfer of the data for the first frame is started before or at the corresponding TE signal).
Re: claims 12 and 24 (which are rejected under the same rationale), Youn and Zhang teach
12. The apparatus of claim 1, wherein the one or more frame content buffers are obtained from a graphics processing unit (GPU),
(“The frame generation subsystem 102 operates to generate a sequence of video frames... for display and includes... one or more graphics processing units (GPUs) 114... The display control subsystem 104... includes a graphics random access memory (GRAM) 118 or other memory operating as a frame buffer... ”; Youn, p. 6, line 27-p. 7, line 7, Fig. 1)
Fig. 1 illustrates that the display system includes a GPU 114 and a graphics random access memory that operates as a frame buffer.
(“As part of this execution process, the CPU 112 directs the GPU 114 to render or otherwise generate each frame in the sequence, and the DPU 116 performs one or more post-rendering processes on the frame... The frame data 131 for the resulting frame 132 is then transmitted to the display control subsystem 104 for buffering in the GRMA 118.”; Youn, p. 7, lines 24-29, Fig. 1)
The GPU renders each frame, and the DPU performs post-rendering processes on the frame. The frame is then transmitted to the GRAM. Thus, the GRAM (frame content buffer) is obtained from a GPU via a DPU.
the fence for the one or more frame content buffers is obtained from the GPU, and the signal for the fence for the one or more content buffers is received from the GPU. (“... a specified signal is provided by the frame generation subsystem 102 to signal completion of rendering of a frame, such as through transmission of a 2C data packet.”; Youn, p. 12, Fig. 1)
Fig. 1 illustrates that the signal indicating frame rendering completion (fence) is provided by the frame generation subsystem, which includes the GPU (the fence for the one or more frame content buffers is obtained from the GPU and the signal for the fence for the one or more content buffers is received from the GPU).
Re: claim 13, Youn and Zhang teach
13. The apparatus of claim 1, wherein the apparatus is a wireless communication device. (“The computer-readable storage medium may be embedded in the computing system... fixedly attached to the computing system... removably attached to the computing system... or coupled to the computer system via a weird or wireless network (e.g., network accessible storage (NAS)). ”; Youn, p. 25, line 30-p. 26, line 3)
The computer system (apparatus) communicates over a wireless network.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Young in view of Zhang as applied to claim 1 above, and further in view of Choudha et al. U.S. Pub. No. 2019/0182452.
Re: claim 11, Youn and Zhang are silent regarding the display is a command mode display, however, Choudha teaches
11. The apparatus of claim 1, wherein the display is a command mode display. (“Display panel 30 may be configured in accordance with the MIPI DSI (Mobile Industry Processor Interface, Display Serial Interface) standard. The MIPI DSI standard supports a video mode and command mode... In examples where display panel 30 is a command mode panel, display panel 30 includes a frame buffer to which display processor 28 writes the image content of the frame. Display processor 28 then writes from the frame buffer to display panel 30.”; Choudha, [0047], Fig. 1)
Fig. 1 illustrates display panel 30, which is a command mode panel. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Youn by adding the feature of the display is a command mode display, in order to reduce the need to refresh the display panel continuously, as taught by Choudha ([0047])
Conclusion
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/Donna J. Ricks/Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618