DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 6, 16, 18, 28, 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 6, 18, 30 recite “each of the multiple ones” and “the multiple ones”. It is not clear what “each” and “the” are referring to. The claim also recites “a selection of multiple ones”. It is not clear how “each” and “the” relate to this selection of multiple ones and is therefore indefinite. Claims 4, 6, 16, 18, 28, 30 recite “are to be applied” or “is to be applied”. However it is not clear if the claim requires applying or not and seems to be merely an intention and is therefore indefinite and unclear. Claim 16 recites “the receiving of the value”. There is insufficient antecedent basis for this limitation in the claim. Examiner notes claim 16 depends on claim 14 not claim 15, which would resolve the issue. For the purpose of examination, Examiner has interpreted claim 16 to depend on claim 15.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 7, 13, 15, 17, 19, 25, 27, 29, 31is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 8,479,130 B1) in view of Vlach (US 5, 548, 539). With respect to Claim 1 Zhang teaches A computer-implemented method comprising (See Abstract): receiving timing data of multiple data paths of an integrated circuit (IC) design (See Col 1 line 63-col2 line1 A typical standard-cell library contains two main components: a Library Database often including layout, schematic, symbol, 65 abstract, and other logical or simulation views, and a Timing Abstract providing functional definitions, timing, power, and noise information for each cell. And See Col 3 lines 58-63 The method 100 includes providing a library 102 of standard cells each having respective definitions of inter-connected devices and pins for connection to other cells and/or ports, the library containing layout and performance data for respective cells.); simulating degradation of the multiple data paths over a period of time, wherein the timing data serve as a baseline of the simulated degradation, (See Col2 line 63-col3 line 17 An instance activity file (IAF) 104 is provided simulating electrical activity at the pins of individual instances of the cells in the IC. TheIAF 104 and the DAF 202 are used to provide a simulation 206 of activity of the devices in the IC and consequent aging evolution of electrical characteristics of the devices.)and wherein the simulation comprises: simulating effects of operational conditions on the multiple data paths, wherein the operational conditions comprise: temperature, voltage, and frequency, (See col 5 line 44-52 The method 100 supports different desired digital timing library based analysis 45 for the aged design, such as the timing, power, thermal analysis and others.) simulating an effect of at least one physical degradation phenomenon on the multiple data paths, wherein the at least one physical degradation phenomenon is selected from the group consisting of: negative-bias temperature instability (NBTI), hot carrier injection (HCI), electromigration (EM), and time-dependent dielectric breakdown (TDDB), (See Col 1 lines 11-23 Semiconductor devices are subject to various phenomena that degrade their performance with use and over time. With the evolution of manufacturing process technology, feature sizes have gotten smaller, currently down to tens of nanometers, which accentuate such degradation. Among such phenomena are hot carrier injection (HCI), negative bias temperature instability (NBTI) and time dependent dielectric (gate oxide) breakdown (TDDB). The resulting changes in device characteristics change the circuit performance and may cause the circuit to fail.)and simulating operation of a margin measurement circuit which is embedded in the IC design and monitors the multiple data paths, wherein the margin measurement circuit, in the simulated operation,; (See Col 3 lines 10-17 and col 5 lines 29-52 The method 100 enables the effects of different reliability phenomena to be merged and obtain the cumulative aged analysis. The method 100 supports different desired digital timing library based analysis 45 for the aged design, such as the timing, power, thermal analysis and others. Users can start the aged analysis from any digital design stage, such as synthesis, floor plan or place & route. The method 100 can generate the aged SDF file 128 for aged simulation. Based on the comparison of fresh and aged 50 design analysis or simulation, designers can debug and/or modify the design to account for expected aging issues.) and based on the simulated degradation, estimating at least one of: a degradation curve of the multiple data paths over the period of time, or a predicted time of failure of the IC design due to a timing violation (See Col2 lines 15-19 It has been pro-posed to simplify the aging calculations by performing the calculations at cell level, from the layout, taking account of HCI effects only, and extrapolating the cell fresh slew rate by a ratio of expected degradation, to obtain the consequences for timing only). However Zhang is silent to the language of outputs a time series of values of a worst-case remaining margin of the multiple data paths by a worst-performing data path of the multiple data paths Nevertheless Vlach teaches outputs a time series of values of a worst-case remaining margin of the multiple data paths (See Col 2 lines1-9 and Col 3 lines 3-8. to be able to perform a worst case analysis on the system, to be able to simulate failure modes and the effects thereof, and to provide a centering and tolerancing analysis. A further object of the invention is to determine minimum and maximum worst case values for device and/or system performance with a defined set of device values and tolerances and to determine, under worst case conditions, whether any devices exceed their specifications or operate outside of their design envelopes.) by a worst-performing data path of the multiple data paths (See Col 2 lines 1-9)
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and output a time series of values of a worst-case remaining margin of the multiple data paths such as that of Vlach. One of ordinary skill would have been motivated to modify Zhang because a worse-case remaining margin would allow one to determine minimum and maximum worst case values for device and/or system performance with a defined set of device values and tolerances and to determine, under worst case conditions, whether any devices exceed their specifications or operate outside of their design envelopes and thus improve efficiency. With respect to Claim 3 Zhang teaches The computer-implemented method of claim 1, further comprising: receiving values of the operational conditions from a user. (See Col 4 lines 32-37) With respect to Claim 5 Zhang teaches The computer-implemented method of claim 1, further comprising: receiving a selection of the at least one physical degradation phenomenon from a user, wherein the simulating of the effect of the at least one physical degradation phenomenon is based on the selection. (See Col 5 lines 44-52) With respect to Claim 7 Zhang is silent to the language of The computer-implemented method of claim 1, wherein: the values of the worst-case remaining margin, which are output by the margin measurement circuit, are each given as a range of worst-case remaining margins. Nevertheless Vlach teaches the values of the worst-case remaining margin, which are output by the margin measurement circuit, are each given as a range of worst-case remaining margins. (See Col 2 lines1-9 and Col 3 lines 3-8..)
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and output a time series of values of a worst-case remaining margin of the multiple data paths such as that of Vlach. One of ordinary skill would have been motivated to modify Zhang because a worse-case remaining margin would allow one to determine minimum and maximum worst case values for device and/or system performance with a defined set of device values and tolerances and to determine, under worst case conditions, whether any devices exceed their specifications or operate outside of their design envelopes and thus improve efficiency. With respect to Claim 13 Zhang teaches A system comprising (See Abstract): (a) at least one hardware processor (See Col3 lines 17-22); and (b) a non-transitory computer-readable storage medium having program code embodied therewith, the program code executable by said at least one hardware processor to: (See Col3 lines 17-22) receive timing data of multiple data paths of an integrated circuit (IC) design; (See Col 1 line 63-col2 line1 A typical standard-cell library contains two main components: a Library Database often including layout, schematic, symbol, 65 abstract, and other logical or simulation views, and a Timing Abstract providing functional definitions, timing, power, and noise information for each cell. And See Col 3 lines 58-63 The method 100 includes providing a library 102 of standard cells each having respective definitions of inter-connected devices and pins for connection to other cells and/or ports, the library containing layout and performance data for respective cells.); automatically simulate degradation of the multiple data paths over a period of time, wherein the timing data serve as a baseline of the simulated degradation, and wherein the simulation comprises: (See Col2 line 63-col3 line 17 An instance activity file (IAF) 104 is provided simulating electrical activity at the pins of individual instances of the cells in the IC. TheIAF 104 and the DAF 202 are used to provide a simulation 206 of activity of the devices in the IC and consequent aging evolution of electrical characteristics of the devices.) simulating effects of operational conditions on the multiple data paths, wherein the operational conditions comprise: temperature, voltage, and frequency, (See col 5 line 44-52 The method 100 supports different desired digital timing library based analysis 45 for the aged design, such as the timing, power, thermal analysis and others.) simulating an effect of at least one physical degradation phenomenon on the multiple data paths, wherein the at least one physical degradation phenomenon is selected from the group consisting of: negative-bias temperature instability (NBTI), hot carrier injection (HCI), electromigration (EM), and time-dependent dielectric breakdown (TDDB), and simulating operation of a margin measurement circuit which is embedded in the IC design and monitors the multiple data paths, wherein the margin measurement circuit, in the simulated operation, and (See Col 1 lines 11-23 Semiconductor devices are subject to various phenomena that degrade their performance with use and over time. With the evolution of manufacturing process technology, feature sizes have gotten smaller, currently down to tens of nanometers, which accentuate such degradation. Among such phenomena are hot carrier injection (HCI), negative bias temperature instability (NBTI) and time dependent dielectric (gate oxide) breakdown (TDDB). The resulting changes in device characteristics change the circuit performance and may cause the circuit to fail.) based on the simulated degradation, estimating at least one of: a degradation curve of the multiple data paths over the period of time, or a predicted time of failure of the IC design due to a timing violation. (See Col2 lines 15-19 It has been pro-posed to simplify the aging calculations by performing the calculations at cell level, from the layout, taking account of HCI effects only, and extrapolating the cell fresh slew rate by a ratio of expected degradation, to obtain the consequences for timing only). However Zhang is silent to the language of outputs a time series of values of a worst-case remaining margin of the multiple data paths by a worst-performing data path of the multiple data paths Nevertheless Vlach teaches outputs a time series of values of a worst-case remaining margin of the multiple data paths (See Col 2 lines1-9 and Col 3 lines 3-8. to be able to perform a worst case analysis on the system, to be able to simulate failure modes and the effects thereof, and to provide a centering and tolerancing analysis. A further object of the invention is to determine minimum and maximum worst case values for device and/or system performance with a defined set of device values and tolerances and to determine, under worst case conditions, whether any devices exceed their specifications or operate outside of their design envelopes.) by a worst-performing data path of the multiple data paths (See Col 2 lines 1-9)
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and output a time series of values of a worst-case remaining margin of the multiple data paths such as that of Vlach. One of ordinary skill would have been motivated to modify Zhang because a worse-case remaining margin would allow one to determine minimum and maximum worst case values for device and/or system performance with a defined set of device values and tolerances and to determine, under worst case conditions, whether any devices exceed their specifications or operate outside of their design envelopes and thus improve efficiency. With respect to Claim 15 Zhang teaches The system of claim 13, wherein the program code is further executable to: receive values of the operational conditions from a user. (See Col 4 lines 32-37) With respect to Claim 17 Zhang teaches The system of claim 13, wherein the program code is further executable to: receive a selection of the at least one physical degradation phenomenon from a user, wherein the simulating of the effect of the at least one physical degradation phenomenon is based on the selection. (See Col 5 lines 44-52) With respect to Claim 19 Zhang is silent to the language of The system of claim 13, wherein: the values of the worst-case remaining margin, which are output by the margin measurement circuit, are each given as a range of worst-case remaining margins. Nevertheless Vlach teaches the values of the worst-case remaining margin, which are output by the margin measurement circuit, are each given as a range of worst-case remaining margins. (See Col 2 lines1-9 and Col 3 lines 3-8..)
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and output a time series of values of a worst-case remaining margin of the multiple data paths such as that of Vlach. One of ordinary skill would have been motivated to modify Zhang because a worse-case remaining margin would allow one to determine minimum and maximum worst case values for device and/or system performance with a defined set of device values and tolerances and to determine, under worst case conditions, whether any devices exceed their specifications or operate outside of their design envelopes and thus improve efficiency. With respect to Claim 25 Zhang teaches A computer program product comprising a non-transitory computer-readable storage medium having program code embodied therewith, the program code executable by at least one hardware processor to(See Col3 lines 17-22): receive timing data of multiple data paths of an integrated circuit (IC) design(See Col 1 line 63-col2 line1 A typical standard-cell library contains two main components: a Library Database often including layout, schematic, symbol, 65 abstract, and other logical or simulation views, and a Timing Abstract providing functional definitions, timing, power, and noise information for each cell. And See Col 3 lines 58-63 The method 100 includes providing a library 102 of standard cells each having respective definitions of inter-connected devices and pins for connection to other cells and/or ports, the library containing layout and performance data for respective cells.); automatically simulate degradation of the multiple data paths over a period of time, wherein the timing data serve as a baseline of the simulated degradation, and wherein the simulation comprises: (See Col2 line 63-col3 line 17 An instance activity file (IAF) 104 is provided simulating electrical activity at the pins of individual instances of the cells in the IC. TheIAF 104 and the DAF 202 are used to provide a simulation 206 of activity of the devices in the IC and consequent aging evolution of electrical characteristics of the devices.) simulating effects of operational conditions on the multiple data paths, wherein the operational conditions comprise: temperature, voltage, and frequency, (See col 5 line 44-52 The method 100 supports different desired digital timing library based analysis 45 for the aged design, such as the timing, power, thermal analysis and others.) simulating an effect of at least one physical degradation phenomenon on the multiple data paths, wherein the at least one physical degradation phenomenon is selected from the group consisting of: negative-bias temperature instability (NBTI), hot carrier injection (HCI), electromigration (EM), and time-dependent dielectric breakdown (TDDB), (See Col 1 lines 11-23 Semiconductor devices are subject to various phenomena that degrade their performance with use and over time. With the evolution of manufacturing process technology, feature sizes have gotten smaller, currently down to tens of nanometers, which accentuate such degradation. Among such phenomena are hot carrier injection (HCI), negative bias temperature instability (NBTI) and time dependent dielectric (gate oxide) breakdown (TDDB). The resulting changes in device characteristics change the circuit performance and may cause the circuit to fail.) and simulating operation of a margin measurement circuit which is embedded in the IC design and monitors the multiple data paths, wherein the margin measurement circuit, in the simulated operation, outputs a time series of values of a worst-case remaining margin of the multiple data paths; (See Col 3 lines 10-17 and col 5 lines 29-52 The method 100 enables the effects of different reliability phenomena to be merged and obtain the cumulative aged analysis. The method 100 supports different desired digital timing library based analysis 45 for the aged design, such as the timing, power, thermal analysis and others. Users can start the aged analysis from any digital design stage, such as synthesis, floor plan or place & route. The method 100 can generate the aged SDF file 128 for aged simulation. Based on the comparison of fresh and aged 50 design analysis or simulation, designers can debug and/or modify the design to account for expected aging issues.) and based on the simulated degradation, estimating at least one of: a degradation curve of the multiple data paths over the period of time, or a predicted time of failure of the IC design due to a timing violation by a worst-performing data path of the multiple data paths. (See Col2 lines 15-19 It has been pro-posed to simplify the aging calculations by performing the calculations at cell level, from the layout, taking account of HCI effects only, and extrapolating the cell fresh slew rate by a ratio of expected degradation, to obtain the consequences for timing only) With respect to Claim 27 Zhang teaches The computer program product of claim 25, wherein the program code is further executable to: receive values of the operational conditions from a user. (See Col 4 lines 32-37) With respect to Claim 29 Zhang teaches The computer program product of claim 25, wherein the program code is further executable to: receive a selection of the at least one physical degradation phenomenon from a user, wherein the simulating of the effect of the at least one physical degradation phenomenon is based on the selection. (See Col 5 lines 44-52) With respect to Claim 31 Zhang is silent to the language of The computer program product of claim 25, wherein: the values of the worst-case remaining margin, which are output by the margin measurement circuit, are each given as a range of worst-case remaining margins. Nevertheless Vlach teaches wherein: the values of the worst-case remaining margin, which are output by the margin measurement circuit, are each given as a range of worst-case remaining margins. (See Col 2 lines1-9 and Col 3 lines 3-8..)
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and output a time series of values of a worst-case remaining margin of the multiple data paths such as that of Vlach. One of ordinary skill would have been motivated to modify Zhang because a worse-case remaining margin would allow one to determine minimum and maximum worst case values for device and/or system performance with a defined set of device values and tolerances and to determine, under worst case conditions, whether any devices exceed their specifications or operate outside of their design envelopes and thus improve efficiency.
Claim(s) 2, 14, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 8,479,130 B1) in view of Vlach (US 5, 548, 539) as applied to claims 1, 13, 25 respectively above, and further in view Drogi (US 2020/0162030 A1).
With respect to Claim 2 Zhang is silent to the language of The computer-implemented method of claim 1, wherein the margin measurement circuit comprises: a signal combiner configured to combine signals from the multiple data paths; a signal splitter configured to split the combined signals into two test paths; a delay circuit configured to gradually apply varying levels of delay to signals passing through a first one of the two test paths; a comparation circuit configured to determine the worst-case remaining margin of the multiple data paths, based on a comparison between the first test path and a second one of the two test paths. Nevertheless Drogi teaches wherein the margin measurement circuit comprises: a signal combiner configured to combine signals from the multiple data paths (See Fig 2 and Para[0068]); a signal splitter configured to split the combined signals into two test paths(See Fig 2 and Para[0068]); a delay circuit configured to gradually apply varying levels of delay to signals passing through a first one of the two test paths(See Fig 2 and Para[0068]); a comparation circuit configured to determine the worst-case remaining margin of the multiple data paths, based on a comparison between the first test path and a second one of the two test paths(See Fig 2 and Para[0068]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and have a signal combiner, a signal splitter, a delay circuit and a comparation circuit configured such as that of Drogi. One of ordinary skill would have been motivated to modify Zhang, because having those components would be no more than predictable use of prior art elements according to their established functions. Furthermore these components result in digital modeling circuitry that models the supply voltage filter and operates to digitally compensate the digital signal data for effects of the supply voltage filter, such as distortion and thus improve functionality. With respect to Claim 14 Zhang is silent to the language of The system of claim 13, wherein the margin measurement circuit comprises: a signal combiner configured to combine signals from the multiple data paths; a signal splitter configured to split the combined signals into two test paths; a delay circuit configured to gradually apply varying levels of delay to signals passing through a first one of the two test paths; a comparation circuit configured to determine the worst-case remaining margin of the multiple data paths, based on a comparison between the first test path and a second one of the two test paths. Nevertheless Drogi teaches wherein the margin measurement circuit comprises: a signal combiner configured to combine signals from the multiple data paths (See Fig 2 and Para[0068]); a signal splitter configured to split the combined signals into two test paths(See Fig 2 and Para[0068]); a delay circuit configured to gradually apply varying levels of delay to signals passing through a first one of the two test paths(See Fig 2 and Para[0068]); a comparation circuit configured to determine the worst-case remaining margin of the multiple data paths, based on a comparison between the first test path and a second one of the two test paths(See Fig 2 and Para[0068]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and have a signal combiner, a signal splitter, a delay circuit and a comparation circuit configured such as that of Drogi. One of ordinary skill would have been motivated to modify Zhang, because having those components would be no more than predictable use of prior art elements according to their established functions. Furthermore these components result in digital modeling circuitry that models the supply voltage filter and operates to digitally compensate the digital signal data for effects of the supply voltage filter, such as distortion and thus improve functionality. With respect to Claim 26 Zhang is silent to the language of The computer program product of claim 25, wherein the margin measurement circuit comprises: a signal combiner configured to combine signals from the multiple data paths; a signal splitter configured to split the combined signals into two test paths; a delay circuit configured to gradually apply varying levels of delay to signals passing through a first one of the two test paths; a comparation circuit configured to determine the worst-case remaining margin of the multiple data paths, based on a comparison between the first test path and a second one of the two test paths. Nevertheless Drogi teaches wherein the margin measurement circuit comprises: a signal combiner configured to combine signals from the multiple data paths (See Fig 2 and Para[0068]); a signal splitter configured to split the combined signals into two test paths(See Fig 2 and Para[0068]); a delay circuit configured to gradually apply varying levels of delay to signals passing through a first one of the two test paths(See Fig 2 and Para[0068]); a comparation circuit configured to determine the worst-case remaining margin of the multiple data paths, based on a comparison between the first test path and a second one of the two test paths(See Fig 2 and Para[0068]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and have a signal combiner, a signal splitter, a delay circuit and a comparation circuit configured such as that of Drogi. One of ordinary skill would have been motivated to modify Zhang, because having those components would be no more than predictable use of prior art elements according to their established functions. Furthermore these components result in digital modeling circuitry that models the supply voltage filter and operates to digitally compensate the digital signal data for effects of the supply voltage filter, such as distortion and thus improve functionality.
Claim(s) (4, 6, 8, 9,), (16, 18, 20, 21), (28, 30, 32, 33) is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 8,479,130 B1) in view of Vlach (US 5, 548, 539) as applied to claims 1, 13, 25 respectively above, and further in view Landman (WO2019/097516 A1). With respect to Claim 4 Zhang is silent to the language of The computer-implemented method of claim 3, wherein: the receiving of the values of the operational conditions receiving comprises: receiving different values of at least one of the operational conditions, and receiving a selection of different points in time, during the period of time, at which the different values, respectively, are to be applied; and the computer-implemented method further comprises applying the different values at the selected different point in time during the simulation of the operational conditions. Nevertheless Landman teaches the receiving of the values of the operational conditions receiving comprises: receiving different values of at least one of the operational conditions, and receiving a selection of different points in time, during the period of time, at which the different values, respectively, are to be applied; and the computer-implemented method further comprises applying the different values at the selected different point in time during the simulation of the operational conditions (See Para[0063], [0117]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and receive such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because receiving such values would determine the performance and/or predict future failure of the individual IC. With respect to Claim 6 Zhang is silent to the language of The computer-implemented method of claim 5, wherein: the selection of the at least one physical degradation phenomenon comprises: a selection of multiple ones of the physical degradation phenomena, and a selection of different points in time, during the period of time, at which each of the multiple ones of the physical degradation phenomena, respectively, is to be applied; and the computer-implemented method further comprises applying the multiple ones of the physical degradation phenomena at the selected different point in time during the simulating of the effect of the multiple ones of the physical degradation phenomena. Nevertheless Landman teaches the selection of the at least one physical degradation phenomenon comprises: a selection of multiple ones of the physical degradation phenomena, and a selection of different points in time, during the period of time, at which each of the multiple ones of the physical degradation phenomena, respectively, is to be applied; and the computer-implemented method further comprises applying the multiple ones of the physical degradation phenomena at the selected different point in time during the simulating of the effect of the multiple ones of the physical degradation phenomena. (See Para[0063], [0117]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and select such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because selecting such values would determine the performance and/or predict future failure of the individual IC. With respect to Claim 8 Zhang is silent to the language of The computer-implemented method of claim 1, wherein the simulation of the degradation further comprises: simulating execution by the IC of different software applications at different times, by periodically adjusting one or more margin values of one or more of the multiple data paths, respectively. Nevertheless Landman teacheswherein the simulation of the degradation further comprises: simulating execution by the IC of different software applications at different times, by periodically adjusting one or more margin values of one or more of the multiple data paths, respectively. (See Para[0125]-[139]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and simulate such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because simulating would determine the performance and/or predict future failure of the individual IC. With respect to Claim 9 Zhang is silent to the language of The computer-implemented method of claim 1, further comprising, based on the simulated degradation: adjusting one or more of the multiple data paths in the IC design, to increase or decrease the margin of the one or more data paths. Nevertheless Landman teaches based on the simulated degradation: adjusting one or more of the multiple data paths in the IC design, to increase or decrease the margin of the one or more data paths. (See Para[0125]-[139]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and simulate such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because simulating would determine the performance and/or predict future failure of the individual IC. With respect to Claim 16 Zhang is silent to the language of The system of claim 14, wherein: the receiving of the values of the operational conditions receiving comprises: receiving different values of at least one of the operational conditions, and receiving a selection of different points in time, during the period of time, at which the different values, respectively, are to be applied; and the program code is further executable to apply the different values at the selected different point in time during the simulation of the operational conditions. Nevertheless Landman teaches the receiving of the values of the operational conditions receiving comprises: receiving different values of at least one of the operational conditions, and receiving a selection of different points in time, during the period of time, at which the different values, respectively, are to be applied; and the computer-implemented method further comprises applying the different values at the selected different point in time during the simulation of the operational conditions (See Para[0063], [0117]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and receive such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because receiving such values would determine the performance and/or predict future failure of the individual IC. With respect to Claim 18 Zhang is silent to the language of The system of claim 17, wherein: the selection of the at least one physical degradation phenomenon comprises: a selection of multiple ones of the physical degradation phenomena, and a selection of different points in time, during the period of time, at which each of the multiple ones of the physical degradation phenomena, respectively, is to be applied; and the program code is further executable to apply the multiple ones of the physical degradation phenomena at the selected different point in time during the simulating of the effect of the multiple ones of the physical degradation phenomena. Nevertheless Landman teaches
the selection of the at least one physical degradation phenomenon comprises: a selection of multiple ones of the physical degradation phenomena, and a selection of different points in time, during the period of time, at which each of the multiple ones of the physical degradation phenomena, respectively, is to be applied; and the computer-implemented method further comprises applying the multiple ones of the physical degradation phenomena at the selected different point in time during the simulating of the effect of the multiple ones of the physical degradation phenomena.
(See Para[0063], [0117]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and select such as that of Landman.
One of ordinary skill would have been motivated to modify Zhang, because selecting such values would determine the performance and/or predict future failure of the individual IC.
With respect to Claim 20 Zhang is silent to the language of The system of claim 13, wherein the simulation of the degradation further comprises: simulating execution by the IC of different software applications at different times, by periodically adjusting one or more margin values of one or more of the multiple data paths, respectively. Nevertheless Landman teaches wherein the simulation of the degradation further comprises: simulating execution by the IC of different software applications at different times, by periodically adjusting one or more margin values of one or more of the multiple data paths, respectively. (See Para[0125]-[139]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and simulate such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because simulating would determine the performance and/or predict future failure of the individual IC. With respect to Claim 21 Zhang is silent to the language of The system of claim 13, wherein the program code is further executable, based on the simulated degradation, to: adjust one or more of the multiple data paths in the IC design, to increase or decrease the margin of the one or more data paths. Nevertheless Landman teaches based on the simulated degradation: adjusting one or more of the multiple data paths in the IC design, to increase or decrease the margin of the one or more data paths. (See Para[0125]-[139]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and simulate such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because simulating would determine the performance and/or predict future failure of the individual IC. With respect to Claim 28 Zhang is silent to the language of The computer program product of claim 27, wherein: the receiving of the values of the operational conditions receiving comprises: receiving different values of at least one of the operational conditions, and receiving a selection of different points in time, during the period of time, at which the different values, respectively, are to be applied; and the program code is further executable to apply the different values at the selected different point in time during the simulation of the operational conditions. Nevertheless Landman teaches the receiving of the values of the operational conditions receiving comprises: receiving different values of at least one of the operational conditions, and receiving a selection of different points in time, during the period of time, at which the different values, respectively, are to be applied; and the computer-implemented method further comprises applying the different values at the selected different point in time during the simulation of the operational conditions (See Para[0063], [0117]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and receive such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because receiving such values would determine the performance and/or predict future failure of the individual IC. With respect to Claim 30 Zhang is silent to the language of The computer program product of claim 29, wherein: the selection of the at least one physical degradation phenomenon comprises: a selection of multiple ones of the physical degradation phenomena, and a selection of different points in time, during the period of time, at which each of the multiple ones of the physical degradation phenomena, respectively, is to be applied; and the program code is further executable to apply the multiple ones of the physical degradation phenomena at the selected different point in time during the simulating of the effect of the multiple ones of the physical degradation phenomena. Nevertheless Landman teaches
the selection of the at least one physical degradation phenomenon comprises: a selection of multiple ones of the physical degradation phenomena, and a selection of different points in time, during the period of time, at which each of the multiple ones of the physical degradation phenomena, respectively, is to be applied; and the computer-implemented method further comprises applying the multiple ones of the physical degradation phenomena at the selected different point in time during the simulating of the effect of the multiple ones of the physical degradation phenomena.
(See Para[0063], [0117]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and select such as that of Landman.
One of ordinary skill would have been motivated to modify Zhang, because selecting such values would determine the performance and/or predict future failure of the individual IC. With respect to Claim 32 Zhang is silent to the language of The computer program product of claim 25, wherein the simulation of the degradation further comprises: simulating execution by the IC of different software applications at different times, by periodically adjusting one or more margin values of one or more of the multiple data paths, respectively. Nevertheless Landman teaches wherein the simulation of the degradation further comprises: simulating execution by the IC of different software applications at different times, by periodically adjusting one or more margin values of one or more of the multiple data paths, respectively. (See Para[0125]-[139]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and simulate such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because simulating would determine the performance and/or predict future failure of the individual IC. With respect to Claim 33 Zhang is silent to the language of The computer program product of claim 25, wherein the program code is further executable, based on the simulated degradation, to: adjust one or more of the multiple data paths in the IC design, to increase or decrease the margin of the one or more data paths. Nevertheless Landman teaches wherein the program code is further executable, based on the simulated degradation, to: adjust one or more of the multiple data paths in the IC design, to increase or decrease the margin of the one or more data paths. (See Para[0125]-[139]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and simulate such as that of Landman. One of ordinary skill would have been motivated to modify Zhang, because simulating would determine the performance and/or predict future failure of the individual IC.
Claim(s) 10, 22, 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 8,479,130 B1) in view of Vlach (US 5, 548, 539) as applied to claims 1, 13, 25 respectively above, and further in view Liu (US 2005/0134394 A1).
With respect to Claim 10 Zhang is silent to the language of The computer-implemented method of claim 1, further comprising, based on the simulated degradation: receiving data from a margin measurement circuit embedded in an operating IC that was fabricated according to the IC design; and based on the simulated degradation and on the received data, performing at least one of: estimating deviation of actual degradation of the operating IC from the simulated degradation, updating a degradation estimation of the operating IC, or issuing an alert based on an estimated deviation of actual degradation of the operating IC from the simulated degradation. Nevertheless Liu teaches based on the simulated degradation: receiving data from a margin measurement circuit embedded in an operating IC that was fabricated according to the IC design; and based on the simulated degradation and on the received data, performing at least one of: estimating deviation of actual degradation of the operating IC from the simulated degradation, updating a degradation estimation of the operating IC, or issuing an alert based on an estimated deviation of actual degradation of the operating IC from the simulated degradation (See Para[0027][0039],[0041]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and perform estimating, updating, or issuing an alert such as that of Liu. One of ordinary skill would have been motivated to modify Zhang because the degradation levels 216 may be used by the integrated circuit internally in order to adapt to the aging or transistor degradation of its own transistors and thus improve performance. With respect to Claim 22 Zhang is silent to the language of The system of claim 13, wherein the program code is further executable, based on the simulated degradation, to: receive data from a margin measurement circuit embedded in an operating IC that was fabricated according to the IC design; and based on the simulated degradation and on the received data, performing at least one of: estimating deviation of actual degradation of the operating IC from the simulated degradation, update a degradation estimation of the operating IC, or issuing an alert based on an estimated deviation of actual degradation of the operating IC from the simulated degradation. Nevertheless Liu teaches wherein the program code is further executable, based on the simulated degradation, to: receive data from a margin measurement circuit embedded in an operating IC that was fabricated according to the IC design; and based on the simulated degradation and on the received data, performing at least one of: estimating deviation of actual degradation of the operating IC from the simulated degradation, update a degradation estimation of the operating IC, or issuing an alert based on an estimated deviation of actual degradation of the operating IC from the simulated degradation. (See Para[0027][0039],[0041]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and perform estimating, updating, or issuing an alert such as that of Liu. One of ordinary skill would have been motivated to modify Zhang because the degradation levels 216 may be used by the integrated circuit internally in order to adapt to the aging or transistor degradation of its own transistors and thus improve performance. With respect to Claim 34 Zhang is silent to the language of The computer program product of claim 25, wherein the program code is further executable, based on the simulated degradation, to: receive data from a margin measurement circuit embedded in an operating IC that was fabricated according to the IC design; and based on the simulated degradation and on the received data, performing at least one of: estimating deviation of actual degradation of the operating IC from the simulated degradation, updating a degradation estimation of the operating IC, or issuing an alert based on an estimated deviation of actual degradation of the operating IC from the simulated degradation. Nevertheless Liu teaches wherein the program code is further executable, based on the simulated degradation, to: receive data from a margin measurement circuit embedded in an operating IC that was fabricated according to the IC design; and based on the simulated degradation and on the received data, performing at least one of: estimating deviation of actual degradation of the operating IC from the simulated degradation, updating a degradation estimation of the operating IC, or issuing an alert based on an estimated deviation of actual degradation of the operating IC from the simulated degradation. (See Para[0027][0039],[0041]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and perform estimating, updating, or issuing an alert such as that of Liu. One of ordinary skill would have been motivated to modify Zhang because the degradation levels 216 may be used by the integrated circuit internally in order to adapt to the aging or transistor degradation of its own transistors and thus improve performance.
Claim(s) (11, 12), (23, 24), (35, 36) is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 8,479,130 B1) in view of Vlach (US 5, 548, 539) as applied to claims 1, 13, 25 respectively above, and further in view Liu (US 2005/0134394 A1). With respect to Claim 11 Zhang is silent to the language of The computer-implemented method of claim 1, further comprising: in a Dynamic Voltage and Frequency Scaling (DVFS) system of an IC fabricated according to the IC design, configuring parameters of the DVFS system based on the simulated degradation. Nevertheless Anderson teaches in a Dynamic Voltage and Frequency Scaling (DVFS) system of an IC fabricated according to the IC design, configuring parameters of the DVFS system based on the simulated degradation. (See Para[0073]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang use DVFS such as that of Anderson. One of ordinary skill would have been motivated to modify Zhang because DVFS enables trade-offs between power consumption and performance, and thus improve robustness. With respect to Claim 12 Zhang is silent to the language of The computer-implemented method of claim 11, wherein the configuring of the parameters is performed: between when the IC is fabricated and when the IC is released for field operations; and/or during field operation of the IC, at a time determined in advance based on the simulated degradation. Nevertheless Anderson teaches wherein the configuring of the parameters is performed: between when the IC is fabricated and when the IC is released for field operations; and/or during field operation of the IC, at a time determined in advance based on the simulated degradation (See Para[0039]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and configure such as that of Anderson. One of ordinary skill would have been motivated to modify Zhang, because such configuring would allow for appropriate software upgrades to improve efficiency and accuracy. With respect to Claim 23 Zhang is silent to the language of The system of claim 13, wherein the program code is further executable to: in a Dynamic Voltage and Frequency Scaling (DVFS) system of an IC fabricated according to the IC design, configure parameters of the DVFS system based on the simulated degradation. Nevertheless Anderson teaches wherein the program code is further executable to: in a Dynamic Voltage and Frequency Scaling (DVFS) system of an IC fabricated according to the IC design, configure parameters of the DVFS system based on the simulated degradation. (See Para[0073]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang use DVFS such as that of Anderson. One of ordinary skill would have been motivated to modify Zhang because DVFS enables trade-offs between power consumption and performance, and thus improve robustness. With respect to Claim 24 Zhang is silent to the language of The system of claim 23, wherein the configuring of the parameters is performed: between when the IC is fabricated and when the IC is released for field operations; and/or during field operation of the IC, at a time determined in advance based on the simulated degradation. Nevertheless Anderson teaches wherein the configuring of the parameters is performed: between when the IC is fabricated and when the IC is released for field operations; and/or during field operation of the IC, at a time determined in advance based on the simulated degradation (See Para[0039]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and configure such as that of Anderson. One of ordinary skill would have been motivated to modify Zhang, because such configuring would allow for appropriate software upgrades to improve efficiency and accuracy. With respect to Claim 35 Zhang is silent to the language of The computer program product of claim 25, wherein the program code is further executable to: in a Dynamic Voltage and Frequency Scaling (DVFS) system of an IC fabricated according to the IC design, configure parameters of the DVFS system based on the simulated degradation. Nevertheless Anderson teaches wherein the program code is further executable to: in a Dynamic Voltage and Frequency Scaling (DVFS) system of an IC fabricated according to the IC design, configure parameters of the DVFS system based on the simulated degradation. (See Para[0073]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang use DVFS such as that of Anderson. One of ordinary skill would have been motivated to modify Zhang because DVFS enables trade-offs between power consumption and performance, and thus improve robustness. With respect to Claim 36 Zhang is silent to the language of The computer program product of claim 35, wherein the configuring of the parameters is performed: between when the IC is fabricated and when the IC is released for field operations; and/or during field operation of the IC, at a time determined in advance based on the simulated degradation. Nevertheless Anderson teaches wherein the configuring of the parameters is performed: between when the IC is fabricated and when the IC is released for field operations; and/or during field operation of the IC, at a time determined in advance based on the simulated degradation (See Para[0039]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Zhang and configure such as that of Anderson. One of ordinary skill would have been motivated to modify Zhang, because such configuring would allow for appropriate software upgrades to improve efficiency and accuracy.
Conclusion
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YOSHIHISA . ISHIZUKA
Examiner
Art Unit 2857
/YOSHIHISA ISHIZUKA/Primary Examiner, Art Unit 2857
