ACTION
1. This Office Action is responsive to claims filed for App. 18/708,833 on April 13, 2026. Claims 1 and 4-13 are pending. Please note Claim 6 has been withdrawn in light of an earlier restriction requirement.
America Invents Act
2. The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1, 4, 5 and 7-11 rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. ( US 2021/0125561 A1 ).
Choi teaches in Claim 1:
A pixel circuit ( Figure 2, [0066] discloses a pixel P ) comprising:
a first pixel circuit to which a voltage is applied from a driving circuit ( Figure 4, [0068] discloses a first pixel circuit layer 110 which receives driving signals from a scan control line SCL(n) and data line DL );
a second pixel circuit to which a voltage is not directly applied form the driving circuit ( Figure 4, [0069] disclose a second pixel circuit layer 120 which is connected to first pixel circuit layer 110 through a first capacitor C1 providing a voltage, as detailed in [0075]. To clarify, this “a voltage” is applied through the capacitor and not through a scan line, etc ); and
a capacitor formed between the first pixel circuit and the second pixel circuit ( Figure 4, [0075] discloses details of capacitor C1 with first and second terminals C1a and C1b, respectively, formed between 110 and 120, as shown )
wherein a voltage distributed from the first pixel circuit by the capacitor is applied to the second pixel circuit ( Figure 4, [0075] discloses the capacitor C1 passing a voltage through the terminals to 120 ); but
Choi does not explicitly teach “wherein the distributed voltage is determined by an average value according to a position of the second pixel circuit.”
However, Choi teaches in Figure 4 of a capacitance C1 which couples the first and second pixel circuit layers 110 and 120 together, with the capacitor stretched capacitively between C1a/DCE and C1b/UCE. Respectfully, capacitance is based on the distance/position of the second pixel circuit layer 120 and Figures 6, 9, 12, etc, show varying layouts of the two pixel circuit layers relative to each other. Again, this impacts the capacitance between the two circuits. Choi teaches in [0090] and [0085] of capacitance sizing and area of the capacitor C1 relative to the first and second pixel circuits 110 and 120. Respectfully, the distance being an “average value” is a design choice issue in this case given Choi clearly considers the capacitance coupling between the two pixel circuit locations as well as a focus of the capacitance connection/voltage between the two pixel circuits. Given Choi’s emphasis on node locations and designing the two circuit layers in various ways, the value is clearly considered and specifically, the average value therefrom is a design choice issue.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the average position aspects, with the motivation that it is a design choice issue in light of Choi designing different positions for the first and second pixel circuit layers and that the capacitance coupling between them is very dependent on the positioning of the circuit layers.
Choi teaches in Claim 4:
The pixel circuit of claim 1, wherein the first pixel circuit is formed on a first layer of a panel, and the second pixel circuit is formed on a second layer disposed above the first layer. ( Figures 4 and 8, [0183] disclose layers DCE and UCE, formed on first and second layers, respectively. Please note UCE, corresponding to 120, is formed above DCE and 110, as shown )
Choi teaches in Claim 5:
The pixel circuit of claim 4, wherein an electrode of the first pixel circuit and an electrode of the second pixel circuit are connected by a via wire. ( Figure 4 shows a via wire for the terminals of capacitor C1 )
Choi teaches in Claim 7:
The pixel circuit of claim 4, wherein electrodes of the first pixel circuit and electrodes of the second pixel circuit are formed in different numbers. ( Figure 2, [0083] discloses the various elements of 110 and 120 and it is clear that there are a different in the layout of elements, additional elements, etc (read as formed in different numbers) )
Choi teaches in Claim 8:
The pixel circuit of claim 4, wherein an electrode of the first pixel circuit and an electrode of the second pixel circuit are formed in different sizes. ( Figures 2, 6, 9, etc show various layouts of the elements, including different sizes for the pixel circuits 110, 120, etc. Furthermore, Figures 10-12 also show different sizing for elements (read as electrodes) )
Choi teaches in Claim 9:
The pixel circuit of claim 8, wherein the electrode of the first pixel circuit is greater in size than that of the second pixel circuit. ( The same reasoning in Claim 8 is applicable hgere as well: Figures 2, 6, 9, etc show various layouts of the elements, including different sizes for the pixel circuits 110, 120, etc. Furthermore, Figures 10-12 also show different sizing for elements (read as electrodes). TO further clarify, the size of 110 and 120 in general are different from each other, meaning the elements are also different sizes )
Choi teaches in Claim 10:
The pixel circuit of claim 8, wherein the electrode of the first pixel circuit and the electrode of the second pixel circuit at least partially overlap each other. ( Figure 4, [0168] disclose the overlap aspects of 110 and 120. Furthermore, several other figures show the breakdown of the circuits, including the overlap, such as Figure 3 )
Choi teaches in Claim 11:
A micro-display device comprising:
the pixel circuit of claim 1; and a pixel driving circuit configured to apply a voltage to the pixel circuit. ( [0131] disclose a micro light emitting diode device and Figure 1 shows the driving circuits )
6. Claims 12 and 13 rejected under 35 U.S.C. 103 as being unpatentable over Choi et al.
( US 2021/0125561 A1 ), as applied to Claim 11, further in view of Yoo et al.
( US 2022/0068219 A1 ).
As per Claim 12:
Choi does not explicitly teach of “a pixel compensation preprocessor configured to pre-process an input image according to a driving of an average value of a capacitor coupling; and a resolution converter configured to convert a first resolution of the input image to a second resolution; wherein the pixel driving circuit applies a voltage to the pixel circuit at the converted second resolution.”
Initially, Choi teaches in [0006] of resolution issues in a display and being able to still drive pixels effectively.
To emphasize, in the same field of endeavor, display driving with multiple areas (similar to Choi’s two pixel circuit layers), Yoo teaches in to have multiple resolutions in different areas, ( Yoo, Figures 1-4, [0010] ). Notably, Yoo teaches to have a compensation voltage generation to output compensation voltages that are different according to each resolution (read as a resolution converter). Yoo teaches in Figure 6 of a pixel circuit similar to Choi as well. As combined, there is provided a resolution compensation/consideration and to be able to compensate the pixel areas according to resolution changes.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the resolution compensation aspects, as taught by Yoo, with the motivation that each area c an improve a brightness difference and a color difference between low and high resolution pixels, ( Yoo, [0006] ).
Yoo teaches in Claim 13:
The micro display device of claim 12, wherein the second resolution is less than the first resolution. ( [0038] discloses the second resolution is lower than a first resolution )
Response to Arguments
7. Applicant’s arguments considered, but are respectfully not persuasive.
Please note the updated rejection in light of the claim amendments.
Applicant argues Choi does not teach of using the average value of the position of the second pixel circuit. However, Choi teaches of a capacitor providing a distributed voltage between the first and second pixel circuit and teaches in [0085] and [0090] of aspects of designing the capacitor to provide that distributed voltage. Respectfully, capacitance is a function of position/distance between elements, in this case, the pixel circuit. Furthermore, please note the obviousness type reasoning and one of ordinary skill in the art would be motivated to design the capacitor, and thus the capacitance voltage, based on the position of the first and second pixel circuits. Choi already teaches of this concept and it being the average value is a design choice issue. Examiner disagrees that the unique threshold voltage of the specific pixel would mix with surrounding pixels given the capacitor specifically connects two adjacent pixel circuits, which are overlaid together. There is no reason to think there would be any effect on surrounding pixels.
Looking at Applicant’s disclosure, the average position is relevant in the sense that there are surrounding pixels, but the claim language does not provide detail/definition/context for these aspects. Applicant is advised to better claim these aspects to overcome the current rejection.
Conclusion
8. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621
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