DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
01/16/2026 has been entered.
Response to Amendment
The office action is responding to the arguments filed on 01/16/2026. Claims 1-
11 are pending. Applicant’s amendments for claims 9 and 10 are considered and rejection of 35 U.S.C. 112(b) is hereby withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 7-11 are rejected under 35 U.S.C. 103 as being unpatentable
over Tsai et al. (US 20160364179 A1) in view of RICHTER et al. (US 20220043570 A1) hereinafter Tsai and RICHTER.
Regarding claim 1, Tsai teaches A storage control method applied to a storage controller: wherein and where first queue is configured to perform information interaction between the host and the storage controller (See Fig. 2, paragraph [0028], illustrates a method for command queuing in a memory system where queued command request 240 indicates plurality of queued requests and where information as queued command request 240-1 are exchanged between host and memory system)
sending, to the host, one command acquisition request for the first queue, (See Fig. 4B, paragraph [0034], illustrates memory system 404 can send a data transfer request 452-1, which includes a direction bit to indicate the direction of data transfer during execution of the command, to the host 402)
Tsai teaches Flash storage control method for command queue management. However, Tsai does not explicitly teach
wherein the one command acquisition request corresponds to and is configured to response to the plurality of queue request messages that is accumulated in the first queue; and
receiving, from the host, storage commands which are sent by the host in response to the one command acquisition request and corresponding to the plurality of queue request messages that is accumulated in the first queue, in one-time transfer.
On the other hand, RICHTER which also relates to storage control method for command queue management teaches wherein the one command acquisition request corresponds to and is configured to response to the plurality of queue request messages that is accumulated in the first queue; and (See Fig. 3A, paragraph [0047] and [0048], illustrates at step 1 a “queue command” is used to gather commands in submission queue and a notice is served by host to memory device that commands are accumulated in submission queue)
receiving, from the host, storage commands which are sent by the host in response to the one command acquisition request and (See Fig. 3A, paragraph [0051] and [0054], illustrates at step 2 the memory device can obtain or receive all of the new commands accumulated in the submission queue 304)
corresponding to the plurality of queue request messages that is accumulated in the first queue, in one-time transfer (See Fig. 6, paragraph [0085], illustrates a flow chart 600 of a method of fetch coalescing where at step 606, memory device determines whether to coalesce the fetching based on the analysis and if yes then fetching or transfer of commands is done fully coalescing or all at once)
Both Tsai and RICHTER relate storage control method for command queue
Management (see Tsai, abstract, and see RICHTER, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Tsai with RICHTER by incorporating storage control method for command queue management, as taught by RICHTER, to illustrate at step 1 a “queue command” is used to gather commands in submission queue and a notice is served by host to memory device that commands are accumulated in submission queue and at step 2 the memory device can obtain or receive all of the new commands accumulated in the submission queue 304 and a flow chart 600 of a method of fetch coalescing where at step 606, memory device determines whether to coalesce the fetching based on the analysis and if yes then fetching or transfer of commands is done fully coalescing or all at once. The combined system of Tsai – RICHTER allows adding intelligence in the memory device (separate from or in addition to the intelligence on the host device) as to when to fetch the commands may more efficiently implement the process of fetching commands from the submission queue as mentioned in paragraph [0021]. Therefore, the combination of Tsai - RICHTER improves the process of fetching commands. See RICHTER, paragraph [0021].
Regarding claim 2, Tsai in view of RICHTER teaches storage control method for command queue management in claim 1. However, Tsai - RICHTER combination does not explicitly teach The storage control Method of claim 1, wherein before sending the command acquisition request for the first queue to the host, the storage control method further comprises: determining a queue corresponding to a flag register which is enabled in a first flag register table of at least one flag register table as the at least one first queue, wherein each of the at least one flag register table comprises a plurality of flag registers respectively corresponding to the plurality of queues, and
the flag register which is enabled represents that the corresponding queue has accumulated a plurality of queue request message.
On the other hand, Tsai which also relates to storage control method for command queue management teaches The storage control Method of claim 1, wherein before sending the command acquisition request for the first queue to the host, the storage control method further comprises: determining a queue corresponding to a flag register which is enabled in a first flag register table of at least one flag register table as the at least one first queue, wherein each of the at least one flag register table comprises a plurality of flag registers respectively corresponding to the plurality of queues, and (See Fig. 1 and 2, paragraph [0022] and paragraph [0028], illustrates status register 127 and command description register 244 can be registers that stores status information which may include command enabled or not for each of the commands in the command queue 126)
the flag register which is enabled represents that the corresponding queue has accumulated a plurality of queue request message. (See Fig. 2, paragraph [0028], illustrates command descriptor block 244 includes information regarding the command that enables the host 202 and the memory system 204 to execute the command when they are ready to execute commands)
The same motivation that was utilized for combining Tsai and RICHTER
as set forth in claim 1 is equally applicable to claim 2.
Regarding claim 7, Tsai in view of RICHTER teaches storage control method for command queue management in claim 1. However, Tsai - RICHTER combination does not explicitly teach The storage control method of claim 1, wherein sending the command acquisition request for the first queue to the host comprises: generating a command acquisition request for the any first queue according to the plurality of queue request messages of the first queue that is accumulated in the first queue, wherein a number of storage commands corresponding to the command acquisition request for the any first queue is equal to a sum of numbers of storage commands corresponding to all the plurality of queue request messages of the first queue that is accumulated in the first queue; and sending the command acquisition request for the any first queue.
On the other hand, Tsai which also relates to storage control method for
command queue management teaches The storage control method of claim 1, wherein sending the command acquisition request for the first queue to the host comprises: generating a command acquisition request for the any first queue according to the plurality of queue request messages of the first queue that is accumulated in the first queue, wherein a number of storage commands corresponding to the command acquisition request for the any first queue is equal to a sum of numbers of storage commands corresponding to all the plurality of queue request messages of the first queue that is accumulated in the first queue; and sending the command acquisition request for the any first queue. (See Fig. 2, paragraph [0028], illustrates if the command queue in the memory system 204 is ready to receive commands to add to the command queue the memory system 204 can send command response 242-0 with the queue busy bit set to zero (0) to the host 202 indicating that the memory system 204 is ready to add commands to the command queue. In other words, memory system is ready to add more commands to the queue if busy bit is zero and total number of commands should be the sum of all commands)
The same motivation that was utilized for combining Tsai with RICHTER as set forth in claim 1 is equally applicable to claim 7.
Regarding claim 8, Tsai in view of RICHTER teaches storage control method for command queue management in claim 1. However, Tsai - RICHTER combination does not explicitly teach A storage controller, comprising: one or more processing units; and a storage unit having stored thereon one or more programs which, when executed by the one or more processing units, cause the one or more processing units to implement the storage control method of claim 1
On the other hand, Tsai which also relates to storage control method for
command queue management teaches A storage controller, comprising: one or more processing units; and a storage unit having stored thereon one or more programs which, when executed by the one or more processing units, cause the one or more processing units to implement the storage control method of claim 1. (See Fig 1, Fig. 2, paragraph [0019], paragraph [0028], illustrate host 102 may include a
number of processors along with the controller 125 implementing the method of queuing
commands)
The same motivation that was utilized for combining Tsai with RICHTER as set forth in claim 1 is equally applicable to claim 8.
Regarding claim 9, Tsai in view of RICHTER teaches storage control method for command queue management in claim 1. However, Tsai - RICHTER combination does not explicitly teach A storage chip, comprising: a storage controller; and a memory, wherein the storage controller comprises: one or more processing units: and a storage unit having stored thereon one or more programs which, when executed by the one or more processing units, cause the one or more processing units to implement the storage control method of claim 1
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches A storage chip, comprising: a storage controller; and a memory, wherein the storage controller comprises: one or more processing units: and a storage unit having stored thereon one or more programs which, when executed by the one or more processing units, cause the one or more processing units to implement the storage control method of claim 1. (See Fig 2A, paragraph [0030], illustrate controller 102 may have modules which may include memory hardware that comprises instructions executable with a processor or processor circuitry to implement one or more of the features of the module)
Both Tsai and RICHTER relate storage control method for command queue
Management (see Tsai, abstract, and see RICHTER, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Tsai with RICHTER by incorporating storage control method for command queue management, as taught by RICHTER, to illustrate controller 102 may have modules which may include memory hardware that comprises instructions executable with a processor or processor circuitry to implement one or more of the features of the module. The combined system of Tsai – RICHTER allows adding intelligence in the memory device (separate from or in addition to the intelligence on the host device) as to when to fetch the commands may more efficiently implement the process of fetching commands from the submission queue as mentioned in paragraph [0021]. Therefore, the combination of Tsai - RICHTER improves the process of fetching commands. See RICHTER, paragraph [0021].
Regarding claim 10, Tsai in view of RICHTER teaches storage control method for command queue management in claim 1. However, Tsai - RICHTER combination does not explicitly teach A network card, comprising: a main control chip and a storage chip, wherein the storage chip comprises a storage controller wherein the storage chip comprises the a storage controller of wherein the storage controller comprises: one or more processing units and a storage unit having stored thereon one or more programs which, when executed by the one or more processing units, cause the one or more processing units to implement the storage control method of claim 1
On the other hand, Tsai which also relates to storage control method for
command queue management teaches A network card, comprising: a main control chip and a storage chip, wherein the storage chip comprises a storage controller wherein the storage chip comprises the a storage controller of wherein the storage controller comprises: one or more processing units and a storage unit having stored thereon one or more programs which, when executed by the one or more processing units, cause the one or more processing units to implement the storage control method of claim 1. (See Fig 2A, paragraph [0030], illustrate controller 102 may have modules which may include memory hardware that comprises instructions executable with a processor or processor circuitry to implement one or more of the features of the module)
Both Tsai and RICHTER relate storage control method for command queue
Management (see Tsai, abstract, and see RICHTER, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Tsai with RICHTER by incorporating storage control method for command queue management, as taught by RICHTER, to illustrate controller 102 may have modules which may include memory hardware that comprises instructions executable with a processor or processor circuitry to implement one or more of the features of the module. The combined system of Tsai – RICHTER allows adding intelligence in the memory device (separate from or in addition to the intelligence on the host device) as to when to fetch the commands may more efficiently implement the process of fetching commands from the submission queue as mentioned in paragraph [0021]. Therefore, the combination of Tsai - RICHTER improves the process of fetching commands. See RICHTER, paragraph [0021].
Regarding claim 11, Tsai in view of RICHTER teaches storage control method for command queue management in claim 1. However, Tsai - RICHTER combination does not explicitly teach A non-transitory computer-readable medium storing a computer program which, when executed by a processor, implements the storage control method of claim 1
On the other hand, Tsai which also relates to storage control method for
command queue management teaches A non-transitory computer-readable medium storing a computer program which, when executed by a processor, implements the storage control method of claim 1 (See Fig 1, paragraph [0020], illustrates controller 125 may include hardware and firmware, software for controlling access to the memory to implement the method of commands queue)
The same motivation that was utilized for combining Tsai with RICHTER as set forth in claim 1 is equally applicable to claim 11.
Claim(s) 3-6 are rejected under 35 U.S.C. 103 as being unpatentable
over Tsai et al. (US 20160364179 A1) in view of RICHTER et al. (US 20220043570 A1) and further in view of MIZUNO et al. (US 20190339905 A1) hereinafter Tsai and RICHTER and MIZUNO.
Regarding claim 3, Tsai in view of RICHTER teaches The storage control method of claim 2, further comprising: in response to a queue request message for enabling a flag register corresponding to the second queue in a second flag register table of the at least one flag register table, wherein the second queue is a queue corresponding to a flag register which is disenabled in the first flag register table. (See Fig. 2, paragraph [0028], illustrates host 202 receives command response 242 with a queue busy bit set to one (1) or queue busy bit set to zero (0) indicating if the memory system 204 is enabled or disabled to add commands to command queue)
Tsai in view of RICHTER teaches storage control method for command queue management above. However, Tsai - RICHTER combination does not explicitly teach a second queue,
On the other hand, MIZUNO which also relates to storage control method for command queue management teaches a second queue (See Fig. 6, paragraph [0100], illustrates plurality of queues with second queue being 610C, 612C designated as completion queues for posting completion of the commands)
Both Tsai, MIZUNO and RICHTER relate storage control method for command
Queue Management (see Tsai, abstract, see MIZUNO, abstract, and see RICHTER, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Tsai - RICHTER combination with MIZUNO by incorporating storage control method for command queue management with flag register, as taught by MIZUNO, to enable plurality of queues with second queue being 610C, 612C designated as completion queues for posting completion of the commands. The combined system of Tsai - KANG – RICHTER allows the controller to post the command requiring a faster processing among commands for the storage device in the command queue with a higher priority as mentioned in paragraph [0017]. Therefore, the combination of Tsai - KANG - RICHTER improves processing performance. See MIZUNO, paragraph [0018].
Regarding claim 4, Tsai in view of RICHTER and further in view of MIZUNO teaches storage control method for command queue management in claim 3. However, Tsai - RICHTER - MIZUNO combination does not explicitly teach The storage control method of claim 3, further comprising: in response to a plurality of queue request messages for first queue, determining whether a command acquisition request for the first queue is sent; and when the command acquisition request for the first queue is sent, enabling a flag register corresponding to the any first queue in the second flag register table
On the other hand, Tsai which also relates to storage control method for command queue management teaches The storage control method of claim 3, further comprising: in response to a plurality of queue request messages for first queue, determining whether a command acquisition request for the first queue is sent; and when the command acquisition request for the first queue is sent, enabling a flag register corresponding to the any first queue in the second flag register table. (See Fig. 2, paragraph [0028], illustrates host 202 receives command response a queue busy bit set to zero (0) indicating the memory system 204 is enabled to add commands to command queue)
The same motivation that was utilized for combining Tsai – RICHTER combination with MIZUNO as set forth in claim 3 is equally applicable to claim 4.
Regarding claim 5, Tsai in view of RICHTER and further in view of MIZUNO teaches storage control method for command queue management in claim 3. However, Tsai - RICHTER - MIZUNO combination does not explicitly teach The storage control method of The storage control method of claim 3, wherein after sending the command acquisition request for each first queue to the host, the storage control method further comprises: after a command acquisition request for the any first queue is sent, clearing a flag register corresponding to the any first queue in the first flag register table. Also, Tsai does not teach after command selection is processed or fetched command selection flag turns to zero or cleared to zero.
On the other hand, MIZUNO which also relates to storage control method for
command queue management teaches The storage control method of The storage control method of claim 3, wherein after sending the command acquisition request for each first queue to the host, the storage control method further comprises: after a command acquisition request for the any first queue is sent, clearing a flag register corresponding to the any first queue in the first flag register table. (See Fig. 7, 10 and 13, paragraph [0156], when command queues are not selected are done processing flag turns to 0 for that command. In other words, after command selection is processed or fetched command selection flag turns to zero or cleared to zero)
Both Tsai, MIZUNO and RICHTER relate storage control method for command
Queue Management (see Tsai, abstract, see MIZUNO, abstract, and see RICHTER, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Tsai - RICHTER combination with MIZUNO by incorporating storage control method for command queue management with flag register, as taught by MIZUNO, to enable a method of command selection after it is processed or fetched command selection flag turns to zero or cleared to zero. The combined system of Tsai - RICHTER – MIZUNO allows the controller to post the command requiring a faster processing among commands for the storage device in the command queue with a higher priority as mentioned in paragraph [0017]. Therefore, the combination of Tsai - RICHTER - MIZUNO improves processing performance. See MIZUNO, paragraph [0018].
Regarding claim 6, Tsai in view of RICHTER and further in view of MIZUNO teaches storage control method for command queue management in claim 5. However, Tsai - RICHTER - MIZUNO combination does not explicitly teach The storage control method of claim 5, further comprising: in a case where all flag registers in the first flag register table are cleared, taking a flag register table used as the second flag register table as the first flag register table. Also, Tsai does not teach after all selected commands selection fetched all flags turn to zero or cleared to zero in the table.
On the other hand, MIZUNO which also relates to storage control method for
command queue management teaches The storage control method of claim 5, further comprising: in a case where all flag registers in the first flag register table are cleared, taking a flag register table used as the second flag register table as the first flag register table. (See Fig. 7, 10 and 13, paragraph [0156], when command queues are fetched for processing flag turns to 0 initialized. In other words, after all selected commands selection are fetched all flags turn to zero or cleared to zero in the table)
Both Tsai, MIZUNO and RICHTER relate storage control method for command
Queue Management (see Tsai, abstract, see MIZUNO, abstract, and see RICHTER, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Tsai - RICHTER combination with MIZUNO by incorporating storage control method for command queue management with flag register, as taught by MIZUNO, to enable a method where after all selected commands selection are fetched all flags turn to zero or cleared to zero in the table. The combined system of Tsai - RICHTER – MIZUNO allows the controller to post the command requiring a faster processing among commands for the storage device in the command queue with a higher priority as mentioned in paragraph [0017]. Therefore, the combination of Tsai - RICHTER - MIZUNO improves processing performance. See MIZUNO, paragraph [0018].
Response to Arguments
Applicant’s arguments filed on 05/20/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claim 1 amendments mapping by
primary and secondary references in page 6 of the response: Claim 1 refers to a method applied to a storage controller.
The step "sending, to the host, one command acquisition request for the first queue" in claim 1 recites that the storage controller sends one command acquisition request to the host, and the one command acquisition request corresponds to and is configured to response to the plurality of queue request messages accumulated in the first queue.
None of Tsai and KANG discloses or teaches the above sending step in claim 1..
In summary, applicant argued that primary reference Tsai and secondary references KANG do not teach amended limitations sending one command acquisition to the host. Examiner respectfully disagrees. For further clarification examiner cites portion from Tsai. Also, for applicant’s understanding examiner would like to explain the teachings of Tsai and examiner’s interpretation in more detail here. See Fig. 4B, paragraph [0034], Tsai teaches memory system 404 can send a data transfer request 452-1, which includes a direction bit to indicate the direction of data transfer during execution of the command, to the host 402. The cited portions clearly teach memory system can send a data transfer request to the host. Thus, the rejection of amended claim 1 is maintained.
Applicant’s second argument is claim 1 amendments mapping by
primary and secondary references in page 7 of the response: On the other hand, the step "receiving, from the host, storage commands which are sent by the host in response to the one command acquisition request and correspond to the plurality of queue request messages that is accumulated in the first queue, in one-time transfer" in claim 1 recites that host sends the storage commands in response to the one command acquisition request to the storage controller in one-time transfer, and the storage commands correspond to the plurality of queue request messages that is accumulated in the first queue.
None of Tsai and KANG discloses or teaches the above receiving step in claim 1
In summary, applicant argued that primary reference Tsai and secondary references KANG do not teach amended limitations accumulating request messages or commands in a queue and transfer them in once. The amendment necessitates adding secondary reference RICHTER in this regard. For further clarification examiner cites portion from RICHTER. Also, for applicant’s understanding examiner would like to explain the teachings of RICHTER and examiner’s interpretation in more detail here. See Fig. 3A, paragraph [0051] and [0054], RICHTER teaches at step 2 the memory device can obtain or receive all of the new commands accumulated in the submission queue 304. Also, see Fig. 6, paragraph [0085], RICHTER teaches a flow chart 600 of a method of fetch coalescing where at step 606, memory device determines whether to coalesce the fetching based on the analysis and if yes then fetching or transfer of commands is done fully coalescing or all at once. The cited portions clearly teach memory device can receive all of accumulated commands in queue and coalesce the fetching commands to transfer them all at once. Thus, the rejection of amended claim 1 is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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