DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 06/01/2026 & 05/15/2024 has been considered and placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-11, 13-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Moise et al. (U.S. 2019/0131940).
Regarding claim 1, Moise et al. (hereinafter, Ref~940) discloses (please see Figs. 1-9 and related text for details) an impedance matching stage (e.g., 306 of Fig. 9 can be read as the claimed stage OR at least they are functionally equivalent to it, since it is configured to provide impedance matching for the system) comprising:
an input (disposed at the common node of 316/324/318/320 of Fig. 9) and an output (disposed at the common node of 324/326/328 of Fig. 9);
a short-circuited stub (320/322 of Fig. 9 can be read as the claimed stub) connected to the input;
an open-circuited stub (326 of Fig. 9) connected to the output; and
a series branch (324 of Fig. 9) arranged in between the input and the output;
wherein the short-circuited stub comprises a third transmission line (322 of Fig. 9)meeting claim 1.
Regarding claim 8, Ref~940 supports the claimed “wherein at least one of the short-circuited stub, the open-circuited stub, and the series branch is realized on or in the printed circuit board as described in paragraph [0083], meeting claim 8.
Regarding claim 9, Ref~940 discloses a power amplifier (300 of Fig. 9) comprising:
a main input terminal (e.g., gate of transistor 304 of Fig. 9) for receiving a signal to be amplified;
a main output terminal (load terminal of Fig. 9) for connecting to a load (RL of Fig. 9) and for outputting (via drain of 304 of Fig. 9) the amplified signal to said load;
a power transistor (304 of Fig. 9) having an input terminal (gate of 304 of Fig. 9)and
the impedance matching stage (306 of Fig. 9) according to claim 1, wherein the input of the impedance matching stage is electrically connected to the output terminal of the power transistor, and wherein the output of the impedance matching stage is connected to the main output terminal as seen, meeting claim 9.
Regarding claim 10, Ref~940 discloses the power amplifier according to claim 9, wherein the power amplifier is a switched-mode/class-F power amplifier, meeting claims 10-11.
Regarding claim 13, Ref~940 discloses the power amplifier according to claim 9, further comprising:
a first auxiliary impedance matching network (316 of Fig. 9) arranged in between the output terminal of the power transistor and the input of the impedance matching stage; and/or
a second auxiliary impedance matching network (328 of Fig. 9) arranged in between the output of the impedance matching stage and the main output terminal as seen, meeting claim 13.
Regarding claim 14, Ref~940 supports the claimed “wherein the power transistormeeting claim 14.
Regarding claim 16, Ref~940 discloses a power amplifier (300 of Fig. 9) comprising:
a main input terminal (e.g., 102 of Fig. 1) for receiving a signal to be amplified;
a main output terminal (110 of Fig. 1) for connecting to a load (RL 112 of Fig. 1) and for outputting the amplified signal to said load;
a power transistor (304 of Fig. 9) having an input terminal (gate terminal of 304 of Fig. 9) electrically connected to the main input terminal, and an output terminal (drain of 304 of Fig. 9); and
the impedance matching stage according to claim 8, wherein the input of the impedance matching stage is electrically connected to the output terminal of the power transistor, wherein the output of the impedance matching stage is connected to the main output terminal, and wherein the power transistor is provided as a packaged device or bare semiconductor die mounted on the printed circuit board as described in paragraph [0083], meeting claim 16.
Allowable Subject Matter
Claims 2-7 and 12 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843
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