DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 8/25/26 have been fully considered but they are not persuasive.
Regarding the applicant’s arguments, the applicant states that Koh fails to disclose that the semiconductive layer forms the first electrode and the carrier layer for the deflection element. The examiner respectfully disagrees. Figure 4(f) and the description of Section 3 discloses that the first electrode and the carrier layer share the semiconductive layer. The term “carrier layer” is interpreted as any base layer or component for the deflection element (in this case the mirror).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kah How Koh et al (“Investigation of Piezoelectric drive MEMS mirrors based on single and double S-shaped PZT actuator for 2-D scanning applications”, as cited in IDS dated 5/15/24, “Koh”).
Regarding Claim 1, Koh discloses a micromechanical component (Figures 1-4; page 150, Section “1. Introduction”, last paragraph; page 150, Section “2. Design and Modeling”, first paragraph)
Having a layered structured (Figures 1-4; Page 150, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, second paragraph), and
At least one piezoelectric element (Figures 1-4; Page 150, Section “2. Design and Modeling”, first paragraph),
Containing a first electrode and a second electrode (Figure 1(a), first electrode is the bottom electrode, second electrode is the top electrode) for at least one generating or detecting deflections of a deflection element (Figure 1(a), deflection element is the mirror plate) to a holder (Figure 1(a), the mount is the dual in-line package), wherein the layered structure comprises:
A silicon substrate (Figure 4 discloses an SOI wafer);
A conductive semiconductor layer (Figure 4 discloses a silicon device layer with Pt/Ti thin films);
A piezoelectric layer (Figure 4, piezoelectric layer PZT); and
A conductive layer film (Figure 4, conductive layer film SiO2 layer with Pt), wherein
The conductive semiconductor layer forms the first electrode (Figure 4, the Pt/Ti layer of the conductive semiconductor layer forms the first electrode), wherein
The conductive layer film forms the second electrode of the at least one piezoelectric element (Figure 4, SiO2 layer with Pt/Ti layer; page 150, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, first and second paragraphs) and wherein
The conductive semiconductor layer also forms a carrier layer for the deflection element (Page 150, Section “2. Design and Modeling”, first and second paragraphs; Page 152, Section “3. Device Microfabrication”, first to third paragraphs; page 157, Section “6. Conclusion”, first paragraph).
Regarding Claim 2, Koh discloses the micromechanical component according to claim 1, wherein the conductive semiconductor layer, the piezoelectric layer and the conductive layer film are formed in layers in different layer planes, wherein the different layer planes have a layer sequence starting from one side of the silicon substrate of the conductive semiconductor layer; the piezoelectric layer, and the conductive layer film wherein at least one of: an additional further semiconductor layer, an insulator layer, or a metal layer is inserted between one or more of the conductive semiconductor layer, the piezoelectric layer, or the conductive layer film (Page 152, Section “3. Device Microfabrication” discloses the sequence and the insertion of a metal layer in the first and second paragraphs).
Regarding Claim 3, Koh discloses the micromechanical component according to claim 1, wherein the deflection element includes a spring structure connected to the holder and a mirror plate suspended from the spring structure, and wherein the conductive semiconductor layer substantially simultaneously forms the carrier layer of at least one of the mirror plate or the spring structure (Figures 1(a)-1(c), 2(a)-2(d) and 9(a)-9(b); Page 150, Section “2. Design and Modeling”, third paragraph to page 152, last paragraph; page 154, Section “5.2. Frequency Response”, first paragraph to page 155, last paragraph).
Regarding Claim 4, Koh discloses the micromechanical component according to claim 3, wherein the conductive layer film also forms a light-reflecting mirror layer or the mirror plate (Page 152, Section “3. Device Microfabrication” discloses using the conductive layer film to form a light-reflecting mirror layer).
Regarding Claim 5, Koh discloses the micromechanical component according to claim 3, wherein the spring structure comprises the conductive semiconductor layer, the piezoelectric layer, and the conductive layer film at least in some areas (Figures 1(a)-1(c), 2(a)-2(d) and 9(a)-9(b); Page 150, Section “2. Design and Modeling”, third paragraph to page 152, last paragraph; page 154, Section “5.2. Frequency Response”, first paragraph to page 155, last paragraph).
Regarding Claim 6, Koh discloses the micromechanical component according to claim 5, wherein the conductive semiconductor layer, the piezoelectric layer, and the conductive layer film of the spring structure are located at positions with small bending radii when the spring structure is deflected from a plane to a rest position (Figures 1(a)-1(c), 2(a)-2(d) and 9(a)-9(b); Page 150, Section “2. Design and Modeling”, third paragraph to page 152, last paragraph; page 154, Section “5.2. Frequency Response”, first paragraph to page 155, last paragraph).
Regarding Claim 7, Koh discloses the micromechanical component according to claim 1, wherein the deflection element is formed as a beam element suspended on at least one side, wherein the conductive semiconductor layer also forms the carrier layer of the beam element (Figures 1(a), as annotated below; 4(a)-4(e), 5, and 6; page 150, Section “2. Design and Modeling”, first and second paragraphs; page 152, Section “3. Device Microfabrication”, first to fourth paragraphs).
PNG
media_image1.png
416
592
media_image1.png
Greyscale
Regarding Claim 8, Koh discloses the micromechanical component according to claim 7, wherein the beam element comprises the conductive semiconductor layer, the piezoelectric layer, and the conductive film at least in some areas (Figures 1(a), as annotated in the rejection of claim 7 above, discloses the beam element which is comprised by the conductive semiconductor layer, the piezoelectric layer, and the conductive film, 4(a)-4(e), 5, and 6; page 150, Section “2. Design and Modeling”, first and second paragraphs; page 152, Section “3. Device Microfabrication”, first to fourth paragraphs).
Regarding Claim 9, Koh discloses the micromechanical component according to claim 7, wherein the beam element comprises the silicon substrate, at least in some regions, wherein the silicon substrate is arranged in such a way that it forms an inertial mass for the beam element (Figure 1(a), as annotated in the rejection of claim 1, combined with Figure 4, which discloses the silicon substrate being arranged under the electrodes and piezoelectric layer – this would result in inertial mass being “formed”, since inertial mass is inherently preset in the silicon substrate; Figure 2 discloses the rotation of the beam element, where the last paragraph in page 150 illustrates mode shapes according to the mass matrix).
Regarding Claim 10, Koh discloses the micromechanical component according to claim 1, wherein a passivation layer is arranged at least partially on the piezoelectric layer (Figures 4(a)-4(f); page 152, Section “3. Device Microfabrication”, first and last paragraphs”).
Regarding Claim 11, Koh discloses the micromechanical component according to claim 1, wherein the piezoelectric layer is arranged on the conductive semiconductor layer (Figures 4(a)-4(f); page 152, Section “3. Device Microfabrication”, first and last paragraphs”).
Regarding Claim 12, Koh discloses the micromechanical component according to claim 1, wherein a dielectric layer is arranged between the conductive semiconductor layer and the piezo electric layer, at least in some areas (Figure 4(c); page 152, Section “3. Device Microfabrication”, first paragraph discloses an insulating oxide layer between the piezoelectric layer and the conductive semiconductor layer – “the piezoelectric PZT film was defined using mask 2…an insulating oxide layer was deposited…contact hole formation using 1 um Pt metal lines with Ti adhesion layer was done).
Regarding Claim 13, Koh discloses the micromechanical component according to claim 12, wherein the conductive semiconductor layer is separated from the piezoelectric layer by a dielectric layer, wherein the dielectric layer is formed with full coverage or in regions with an opening area to the conductive semiconductor layer (Figure 4(c); page 152, Section “3. Device Microfabrication”, first paragraph discloses an insulating oxide layer between the piezoelectric layer and the conductive semiconductor layer – “the piezoelectric PZT film was defined using mask 2…an insulating oxide layer was deposited…contact hole formation using 1 um Pt metal lines with Ti adhesion layer was done).
Regarding Claim 14, Koh discloses the micromechanical component according to claim 13, wherein the opening area of the dielectric layer is filled with silicon (Figures 4(a)-4(f) disclose the use of SiO2 as the insulating oxide layer, and page 152, Section “3. Device Microfabrication”, first paragraph discloses an insulating oxide layer between the piezoelectric layer and the conductive semiconductor layer – “the piezoelectric PZT film was defined using mask 2…an insulating oxide layer was deposited…contact hole formation using 1 um Pt metal lines with Ti adhesion layer was done).
Regarding Claim 15, Koh discloses the micromechanical component according to claim 1, wherein the conductive semiconductor layer comprises silicon, in particular polycrystalline silicon (Figures 4(a)-4(f); Page 152, Section “3. Device Microfabrication”, first and second paragraphs).
Regarding Claim 16, Koh discloses the micromechanical component according to claim 1, wherein a metal film is arranged between the piezoelectric layer and the conductive layer film, at least in some areas (Figures 4(a)-4(f); Page 152, Section “3. Device Microfabrication”, second paragraph).
Regarding Claim 17, Koh discloses the micromechanical component according to claim 1, wherein the holder is a chip frame of the micromechanical component (Figure 1(a); Page 150, Section “2. Design and Modeling”, first paragraph).
Regarding Claim 18, Koh discloses the micromechanical component according to claim 1, wherein, for stabilization, a dielectric layer is applied to the second electrode formed by the conductive layer film (Figures 4(a)-4(f); Page 152, Section “3. Device and Microfabrication”, first to third paragraphs).
Regarding Claim 19, Koh discloses a method for producing a micromechanical component (Figures 1(a) and 4(a)-4(f); page 150, Section “1. Introduction”, last paragraph; page 150, Section “2. Design and Modeling”, first paragraph), the method comprising:
Depositing a conductive semiconductor layer on a silicon substrate (Figure 4(a), Si device layer; Figure 1(a), 4(b); page 150, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, first paragraph);
Depositing a piezoelectric layer (Figure 1(a) and 4(a)-4(c), piezoelectric layer PZT; page 152, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, first and second paragraphs);
Depositing a conductive layer film, serving as a second electrode, on the piezoelectric layer (Figure 4(a) SiO2 layer, Pt/Ti thin films; page 150, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, first and second paragraphs); and
Structuring a deflection element by a masking process of the silicon substrate, of the conductive semiconductor layer, of the piezoelectric layer, and of the conductive layer film, by lithographic processes (Figures 1(a), 4(a)-4(e); Page 150, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, first and second paragraphs), wherein
The conductive semiconductor layer is used as a first electrode for the piezoelectric layer and also a carrier layer for the deflection element (Figures 1(a)-1(c), 4(a)-4(f); page 150, Section “2. Design and Modeling”, first and second paragraphs; page 152, Section “3. Device Microfabrication”, first to third paragraphs; page 157, Section “6. Conclusion”, first paragraph).
Regarding Claim 20, Koh discloses the method for producing a micromechanical component according to claim 19, wherein a metal film is deposited on the piezoelectric layer after the piezoelectric layer has been deposited (Figures 4(a)-4(f); Page 152, Section “3. Device Microfabrication”, second paragraph).
Regarding Claim 21, Koh discloses the method for producing a micromechanical component according to claim 20, wherein the metal film is used as a masking for a later structuring process (Figures 4(a)-4(f); Page 152, Section “3. Device Microfabrication”, second paragraph).
Regarding Claim 22, Koh discloses the method for producing a micromechanical component according to claim 19, wherein an auxiliary or sacrificial layer is deposited on the piezoelectric layer after the piezoelectric layer has been deposited and is used as a masking for a later structuring process (Figures 1(a), 4(b)-4(f); page 150, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, first and second paragraphs).
Regarding Claim 23, Koh discloses the method for producing a micromechanical component according to claim 22, wherein the auxiliary or sacrificial layer is formed as a hard mask of silicon nitride (SiN) (Figures 1(a), 4(b)-4(f); page 150, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, first and second paragraphs).
Regarding Claim 24, Koh discloses the method for producing a micromechanical component according to claim 19, wherein a passivation layer is deposited on the piezoelectric layer after the piezoelectric layer has been deposited (Figures 1(a), 4(b)-4(f); page 150, Section “2. Design and Modeling”, first paragraph; page 152, Section “3. Device Microfabrication”, first and second paragraphs).
Regarding Claim 25, Koh discloses the method for producing a micromechanical component according to claim 19, wherein the silicon substrate is formed as an oxidized silicon substrate (Figures 4(a)-4(f); page 152, Section “3, Device Microfabrication”, first and second paragraphs).
Regarding Claim 26, Koh discloses the method for producing a micromechanical component according to claim 19, wherein the masking process of the silicon substrate is performed in such a way that the silicon substrate remains at least partially in a region of the deflection element (Figures 4(b) and 4(f); page 152, Section “3. Device Microfabrication”, first and second paragraphs).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIAM QURESHI whose telephone number is (571)272-4434. The examiner can normally be reached 9AM-5PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Caley can be reached at 571-272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARIAM QURESHI/Examiner, Art Unit 2871
Prosecution Insights