DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Deguchi (US 2012/0019326).
In regard to Claim 12:
Deguchi discloses, in Figure 1, a Doherty amplifier, comprising:
an input terminal (16);
an output terminal (18);
a first main transistor (10, ¶ 0026) provided in a first signal path (10, 22 signal path) connecting the input terminal (16) and the output terminal (18);
a first peak transistor (12, ¶ 0026) provided in a second signal path (12, 24 signal path) connecting the input terminal (16) and the output terminal (18);
a first matching circuit (22) provided in the first signal path (10, 22 signal path); and
a second matching circuit (24) provided in the second signal path (12, 24 signal path),
wherein the first main transistor (10; Figure 8: 11) and the first peak transistor (22; Figure 8: 13) are provided on a first semiconductor chip (Figure 8: 100), and
the first matching circuit (Figure 8: 68a) and the second matching circuit (Figure 8: 68b) are provided on a second semiconductor chip (Figure 8: 60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3-9 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 11,515,842) in view of Deguchi (US 2012/0019326 A1).
In regard to Claim 1:
Wang discloses, in Figure 5, a Doherty amplifier (500), comprising:
an input terminal (502);
an output terminal (504);
a first main transistor (530, Column 3: lines 41-57) provided in a first signal path (520) connecting the input terminal (502) and the output terminal (504);
a second main transistor (560, Column 3: lines 41-57) provided on the output terminal side (560 is connected to the output of 530) of the first main transistor (530) in the first signal path (520);
a first peak transistor (531, Column 3: lines 41-57) provided in a second signal path (521) connecting the input terminal (502) and the output terminal (504); and
a second peak transistor (561, Column 3: lines 41-57) provided on the output terminal side (561 connected to the output of 531) of the first peak transistor (531) in the second signal path (521),
a first main semiconductor chip (Figure 6: 632) and a second peak semiconductor chip (Figure 6: 652), but does not disclose wherein one of the first peak transistor and the second peak transistor, and the first main transistor are provided on a first semiconductor chip, and another of the first peak transistor and the second peak transistor, and the second main transistor are provided on a second semiconductor chip.
Deguchi discloses, in Figure 7, wherein one of the first peak transistor (13) and the second peak transistor, and the first main transistor (11) are provided on a semiconductor chip (100), and another of the first peak transistor and the second peak transistor (13), and the second main transistor (11) are provided on a second semiconductor chip (100; ¶ 0035).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the main (carrier) and peak amplifier dies of Wang with the transistor and chip arrangement taught by Deguchi in order to improve packaging flexibility and obtain the predictable benefits of the semiconductor chip arrangement (Deguchi ¶ 0035-0040).
In regard to Claim 3:
Wang discloses a first main semiconductor chip (Figure 6: 632) and a second peak semiconductor chip (Figure 6: 652), but does not disclose wherein the first peak transistor and the first main transistor are provided on the first semiconductor chip, and the second peak transistor and the second main transistor are provided on the second semiconductor chip.
Deguchi discloses, in Figure 7, wherein the first peak transistor (13) and the first main transistor (11) are provided on the first semiconductor chip (100), and the second peak transistor (13) and the second main transistor (11) are provided on the second semiconductor chip (100).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the main (carrier) and peak amplifier dies of Wang with the transistor and chip arrangement taught by Deguchi in order to improve packaging flexibility and obtain the predictable benefits of the semiconductor chip arrangement (Deguchi ¶ 0035-0040).
In regard to Claim 4:
Wang discloses a first main semiconductor chip (Figure 6: 632) and a second peak semiconductor chip (Figure 6: 652), but does not disclose wherein the second peak transistor and the first main transistor are provided on the first semiconductor chip, and the first peak transistor and the second main transistor are provided on the second semiconductor chip.
Deguchi discloses, in Figure 7, wherein the second peak transistor (13) and the first main transistor (11) are provided on the first semiconductor chip (100), and the first peak transistor (13) and the second main transistor (11) are provided on the second semiconductor chip (100).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the main (carrier) and peak amplifier dies of Wang with the transistor and chip arrangement taught by Deguchi in order to improve packaging flexibility and obtain the predictable benefits of the semiconductor chip arrangement (Deguchi ¶ 0035-0040).
In regard to Claim 5:
All of the claim limitations have been discussed with respect to Claims 1 and 4 above, except for wherein the first main transistor and the first peak transistor have a same gate width, and the second main transistor and the second peak transistor have a same gate width.
Deguchi further discloses wherein the first main transistor and the first peak transistor have a same gate width (¶ 0032), and the second main transistor and the second peak transistor have a same gate width (¶ 0032).
In regard to Claim 6:
All of the claim limitations have been discussed with respect to Claims 1, 4, and 5 above, except for wherein the first semiconductor chip and the second semiconductor chip are semiconductor chips of a same type.
Wang further discloses wherein the first semiconductor chip and the second semiconductor chip are semiconductor chips of a same type (Column 21: 10-20).
In regard to Claim 7:
All of the claim limitations have been discussed with respect to Claims 1 and 3 above, except for wherein a first bonding wire connecting semiconductor chips in the first signal path and a second bonding wire connecting semiconductor chips in the second signal path are not parallel to each other.
Wang further discloses, in Figure 6, wherein a first bonding wire connecting semiconductor chips in the first signal path and a second bonding wire connecting semiconductor chips in the second signal path are not parallel to each other. wherein a first bonding wire (632 bonding wires are horizontally oriented) connecting semiconductor chips (632) in the first signal path (Figure 5: 520) and a second bonding wire (652 bonding wires are vertically oriented) connecting semiconductor chips (652) in the second signal path (Figure 5: 521) are not parallel to each other (the bonding wires of 632 and 652 are perpendicular to one another).
In regard to Claim 9:
All of the claim limitations have been discussed with respect to Claims 1 and 4 above, except for wherein a first bonding wire connecting semiconductor chips in the first signal path and a second bonding wire connecting semiconductor chips in the second signal path are not parallel to each other.
Wang further discloses, in Figure 6, wherein a first bonding wire connecting semiconductor chips in the first signal path and a second bonding wire connecting semiconductor chips in the second signal path are not parallel to each other. wherein a first bonding wire (632 bonding wires are horizontally oriented) connecting semiconductor chips (632) in the first signal path (Figure 5: 520) and a second bonding wire (652 bonding wires are vertically oriented) connecting semiconductor chips (652) in the second signal path (Figure 5: 521) are not parallel to each other (the bonding wires of 632 and 652 are perpendicular to one another).
Claim(s) 13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Deguchi et al. (US 2012/0019326), in view of Wang et al. (US 11,515,842).
In regard to Claim 13:
All of the claim limitations have been discussed with respect to Claim 12 above, except for further comprising: a second main transistor provided on the output terminal side of the first main transistor in the first signal path; and a second peak transistor provided on the output terminal side of the first peak transistor in the second signal path, wherein the second main transistor and the second peak transistor are provided on the first semiconductor chip.
Wang discloses, in Figure 5, further comprising: a second main transistor (560) provided on the output terminal side of the first main transistor (530) in the first signal path (520); and a second peak transistor (561) provided on the output terminal side of the first peak transistor (531) in the second signal path (521), but does not disclose wherein the second main transistor and the second peak transistor are provided on the first semiconductor chip.
Deguchi discloses, in Figure 7, wherein the second main transistor (11) and the second peak transistor (13) are provided on the first semiconductor chip (100).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the main and peak signal paths of Deguchi with the main and peak transistors taught by Wang, in order to have reduced power consumption and power loss, while maintaining or improving efficiency and RF bandwidth (Wang Column 1: lines 23-25).
In regard to Claim 15:
All of the claim limitations have been discussed with respect to Claims 12 and 13 above, except for wherein the first matching circuit is provided between the first main transistor and the second main transistor, in the first signal path, and the second matching circuit is provided between the first peak transistor and the second peak transistor, in the second signal path.
Wang discloses, in Figure 5, wherein the first matching circuit (518) is provided between the first main transistor (530) and the second main transistor (560), in the first signal path (520), and the second matching circuit (519) is provided between the first peak transistor (531) and the second peak transistor (561), in the second signal path (521).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the main and peak signal paths of Deguchi with the matching circuits taught by Wang, in order to have reduced power consumption and power loss, while maintaining or improving efficiency and RF bandwidth (Wang Column 1: lines 23-25).
In regard to Claim 16:
All of the claim limitations have been discussed with respect to Claim 12 above, except for wherein a first bonding wire connecting semiconductor chips in the first signal path and a second bonding wire connecting semiconductor chips in the second signal path are not parallel to each other.
Wang discloses, in Figure 6, wherein a first bonding wire connecting semiconductor chips in the first signal path and a second bonding wire connecting semiconductor chips in the second signal path are not parallel to each other. wherein a first bonding wire (632 bonding wires are hnorizontally oriented) connecting semiconductor chips (632) in the first signal path (Figure 5: 520) and a second bonding wire (652 bonding wires are vertically oriented) connecting semiconductor chips (652) in the second signal path (Figure 5: 521) are not parallel to each other (the bonding wires of 632 and 652 are perpendicular to one another).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the semiconductor chips and packaging layout of Deguchi with the bonding wires taught by Wang, in order to have reduced power consumption and power loss, while maintaining or improving efficiency and RF bandwidth (Wang Column 1: lines 23-25).
Allowable Subject Matter
Claims 2, 8-11, and 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 2:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the first interstage matching circuit and the second interstage matching circuit are provided on a third semiconductor chip.
However, Wang discloses, in Figure 5, a first interstage matching circuit (518) provided between the first main transistor (530) and the second main transistor (560), in the first signal path (520); and a second interstage matching circuit (519) provided between the first peak transistor (531) and the second peak transistor (561), in the second signal path (521).
In regard to Claim 8:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein a first bonding wire and a second bonding wire connecting the first semiconductor chip or the second semiconductor chip to an adjacent semiconductor chip are increased in interval therebetween as approaching the adjacent semiconductor chip.
In regard to Claim 10:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the second peak transistor is longer than the second main transistor in a signal propagation direction, and a drain pad of the second peak transistor is provided adjacent to the second peak transistor in a direction perpendicular to the signal propagation direction.
In regard to Claim 14:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the first main transistor and the first peak transistor are provided inside the second main transistor and the second peak transistor.
Conclusion
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
• LIU et al, US-20250096730 – POWER AMPLIFIER AND METHOD FOR CONTROLLING POWER AMPLIFIER.
• WANG, US-20220123693 – DOHERTY POWER AMPLIFIERS AND DEVICES WITH LOW VOLTAGE.
• Deguchi, US-20120019326 – DOHERTY AMPLIFIER FOR USE AS RADIO COMMUNICATIONS.
• Zhang et al, US-9876474 – DOHERTY POWER AMPLIFIER, COMMUNICATION DEVICE, AND SYSTEM.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIAM SADMAN whose telephone number is (571)270-0921. The examiner can normally be reached M-TH 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
/S.S./Examiner, Art Unit 2843
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