DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a final notice in response to communications received 12/15/2025. Claims 1, 3, 4-13 have been amended. Therefore claims 1-13 are pending and addressed below.
Response to Amendment
Applicant’s amendments and response to the claims are sufficient to overcome 35 USC 112(b) and 35 USC 101 rejections set forth in the previous office action.
Response to Arguments
Applicant’s arguments filed 12/15/2025 have been fully considered and they are not persuasive.
Applicant argues that (1) Belleville does not disclose an alteration of the CPU behavior executing different instructions than the one that has been fetched.
In response to argument (1), Examiner respectfully disagrees. Belleville discloses the code compiled by a compiler is modified by the compiler to include a SGPC…the SGPC includes polymorphism such that at each execution, calling the SGPC may lead to executing a different assembly code…the idea is to obtain a different behavior from one execution to the next one, so that each side-channel observation differs, thus effectively increasing the difficulty to recover the secret data…see section 4.3. The claim’s language does not clarify in S3, and S4, that the behavior of a CPU performing steps S3 and S4 in which the CPU, responsive to a first instruction being fetched in its pipeline, executes second instructions which are different than the first instruction. Therefore, Examiner maintains the same basis of rejections as set forth in the previous office action.
Examiner’s note
Claims 3, 4-11 (claims 5 to 11 are dependent on claim 4) are not rejected under prior art(s).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 12, 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by “NPL: Belleville et al: Automated Software Protection for the Masses Against Side-Channel Attacks” (from Applicant’s IDS)
As per claim 1, Belleville discloses a method for a secure execution of a first instruction by processing means of an electronic system (…see the protections against side-channel attacks…the protection mechanism is based on code polymorphism, so that the observable behavior of the protected component is variable and unpredictable to the attacker…see abstract), comprising: fetching (S1) said first instruction in an execution pipeline of the processing means (…the user starts by annotating the target functions to be secured with polymorphism…see 4.1…the code of a SGPC is composed of a sequence of calls to binary instruction emitters that targets the sequence of ARM assembly instructions generated by the normal compilation flow…see section 4.2, Listing 1), determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack, wherein said first instruction, when executed by the processing means, causes the processing means to perform a first function (…this code is composed of a SGPC for f_critical named SGPC_f_critical and a new function f_critical, which interfaces with the rest of the code…the SGPC of f_critical, SGPC_f_critical, is designed to emit a suite of binary instructions identical to the assembly code that LLVM would have generated for the function (Listing 2)…section 4.2…Odo-runtime currently provides semantic variants for instructions that are frequently used in cryptographic ciphers to manipulate sensitive data…see section 4.3), selecting (S3), based on said determined attack, from an internal memory of said processing means, at least one second instruction, which, when executed by the processing means, causes the processing means to perform a combination of said first function and a dedicated security countermeasure against said determined attack (…semantic variants: some instructions can be replaced by a suite of instructions that achieve the same result and leaves all the originally alive registers unmodified…odo-runtime currently provides semantic variants for instructions that are frequently used in cryptographic ciphers to manipulate sensitive data…instructions belong to the families of eor, sub, load an store, it can be easily extended….odo generates specific function calls to the odo-runtime library for the emission of these instructions when semantic variants is activated…in listing 1, green bold calls are in charge of the emission of semantic variants…at runtime, the SGPC emits the binary code of one variant randomly chosen among available ones…see section 4.3), executing (S4) said selected second instructions instead of said first instruction (…the idea is to obtain a different behavior from one execution to the next one, so that each side-channel observation differs, thus effectively increasing the difficulty to recover the secret data…see Intro, par.2, section 4.3, listing 5).
As per claim 12, Belleville discloses a computer program product directly loadable into the memory of at least one computer, comprising software code instructions for performing a secure execution of a first instruction (…see the protections against side-channel attacks…the protection mechanism is based on code polymorphism, so that the observable behavior of the protected component is variable and unpredictable to the attacker…see abstract) when said product is run on the computer, by fetching (S1) said first instruction in an execution pipeline of the processing means (…the user starts by annotating the target functions to be secured with polymorphism…see 4.1…the code of a SGPC is composed of a sequence of calls to binary instruction emitters that targets the sequence of ARM assembly instructions generated by the normal compilation flow…see section 4.2, Listing 1), determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack, wherein said first instruction, when executed by the processing means, causes the processing means to perform a first function (…this code is composed of a SGPC for f_critical named SGPC_f_critical and a new function f_critical, which interfaces with the rest of the code…the SGPC of f_critical, SGPC_f_critical, is designed to emit a suite of binary instructions identical to the assembly code that LLVM would have generated for the function (Listing 2)…section 4.2…Odo-runtime currently provides semantic variants for instructions that are frequently used in cryptographic ciphers to manipulate sensitive data…see section 4.3), selecting (S3), based on said determined attack, from an internal memory of said processing means, at least one second instruction, which, when executed by the processing means, causes the processing means to perform a combination of said first function and a dedicated security countermeasure against said determined attack (…semantic variants: some instructions can be replaced by a suite of instructions that achieve the same result and leaves all the originally alive registers unmodified…odo-runtime currently provides semantic variants for instructions that are frequently used in cryptographic ciphers to manipulate sensitive data…instructions belong to the families of eor, sub, load an store, it can be easily extended….odo generates specific function calls to the odo-runtime library for the emission of these instructions when semantic variants is activated…in listing 1, green bold calls are in charge of the emission of semantic variants…at runtime, the SGPC emits the binary code of one variant randomly chosen among available ones…see section 4.3), executing (S4) said selected second instructions instead of said first instruction (…the idea is to obtain a different behavior from one execution to the next one, so that each side-channel observation differs, thus effectively increasing the difficulty to recover the secret data…see Intro, par.2, section 4.3, listing 5).
As per claim 13, Belleville discloses an electronic system comprising a processor for performing a secure execution of a first instruction (…see the protections against side-channel attacks…the protection mechanism is based on code polymorphism, so that the observable behavior of the protected component is variable and unpredictable to the attacker…see abstract) by: fetching (S1) said first instruction in an execution pipeline of the processing means (…the user starts by annotating the target functions to be secured with polymorphism…see 4.1…the code of a SGPC is composed of a sequence of calls to binary instruction emitters that targets the sequence of ARM assembly instructions generated by the normal compilation flow…see section 4.2, Listing 1), determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack, wherein said first instruction, when executed by the processing means, causes the processing means to perform a first function (…this code is composed of a SGPC for f_critical named SGPC_f_critical and a new function f_critical, which interfaces with the rest of the code…the SGPC of f_critical, SGPC_f_critical, is designed to emit a suite of binary instructions identical to the assembly code that LLVM would have generated for the function (Listing 2)…section 4.2…Odo-runtime currently provides semantic variants for instructions that are frequently used in cryptographic ciphers to manipulate sensitive data…see section 4.3), selecting (S3), based on said determined attack, from an internal memory of said processing means, at least one second instruction, which, when executed by the processing means, causes the processing means to perform a combination of said first function and a dedicated security countermeasure against said determined attack (…using different transformation used by SGPCs to vary the code of polymorphic instances such as semantic variants…for side-channel attacks countermeasures…some instructions can be replaced by a suite of instructions that achieve the same result and leaves all the originally alive registers unmodified…odo-runtime currently provides semantic variants for instructions that are frequently used in cryptographic ciphers to manipulate sensitive data…instructions belong to the families of eor, sub, load an store, it can be easily extended….odo generates specific function calls to the odo-runtime library for the emission of these instructions when semantic variants is activated…in listing 1, green bold calls are in charge of the emission of semantic variants…at runtime, the SGPC emits the binary code of one variant randomly chosen among available ones…see intro, section 4.3), executing (S4) said selected second instructions instead of said first instruction (…the idea is to obtain a different behavior from one execution to the next one, so that each side-channel observation differs, thus effectively increasing the difficulty to recover the secret data…see Intro, par.2, section 4.3, listing 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over “NPL: Belleville et al: Automated Software Protection for the Masses Against Side-Channel Attacks” (from Applicant’s IDS) in view of Adalier (Pat. No. US 9804891).
As per claim 2, Belleville does not explicitly disclose wherein, said dedicated security counter measure is among variable bounding check, multi memory access and execution desynchronization. However Adalier discloses wherein, said dedicated security counter measure is among variable bounding check (…each execution agent comprises a process or thread bound to a separate compute core in the networking device…each execution agent repeatedly and simultaneously processes next available tasks from the task pool based on priority…each execution agent can be bound to a separate core or processing unit…see col.6 lines 5-8, col. 15 lines 29-31), multi memory access (col.14 line 65-col.15. line 10) and execution desynchronization (…creating and dispatching adjustable “Execution Agents,” which contain asynchronous and duty-specific “worker” routines, specifically optimized to available compute resources, and creates one or more “Task Pool(s)” as staging areas for tasks to be fetched by the Execution Agents…col.15 lines 10-24). Therefore one ordinary skill in the art would have found it obvious before the effective filling date of the claimed invention to use Adalier in Belleville for including the above limitations because one ordinary skill in the art would recognize it would further maintain data integrity, confidentiality and availability while managing a rule-based configuration to serve the network protocol requests…see Adalier, col.15, lines
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (see PTO-form 892).
The following Patents and Papers are cited to further show the state of the art at the time of Applicant’s invention with respect to securing the execution of instructions by processing means of the electronic device.
Best (Pat. No. US 4465901); “Crypto Microprocessor that Executes Enciphered Programs”;
-Teaches an integrated circuit chip having an electronically alterable memory for storing a plurality of executable program instructions and processing circuitry for fetching program instructions from said memory and for executing the fetched instructions and for addressing successor instructions in said memory…see claim 30.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GHAZAL B SHEHNI whose telephone number is (571)270-7479. The examiner can normally be reached Mon-Fri 9am-5pm PCT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Philip Chea can be reached at 5712723951. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GHAZAL B SHEHNI/Primary Examiner, Art Unit 2499