Prosecution Insights
Last updated: April 19, 2026
Application No. 18/711,583

CERAMIC CAPACITOR

Final Rejection §102§103
Filed
May 18, 2024
Examiner
MCFADDEN, MICHAEL P
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Amotech Co. Ltd.
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
701 granted / 815 resolved
+18.0% vs TC avg
Strong +20% interview lift
Without
With
+20.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
25 currently pending
Career history
840
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
33.2%
-6.8% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 815 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4, 8, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Devoe et al (US 2004/0042156). Regarding claim 1, Devoe discloses a ceramic capacitor (Fig. 1-20) comprising: a ceramic body (Fig. 9A, 65) in which a plurality of first dielectric layers (Fig. 9A, at 60) are stacked; and first and second bottom electrodes (Fig. 9A, 72/74) disposed on both sides of a lower surface of the ceramic body (Fig. 9A), wherein the ceramic body further comprises a second dielectric layer (Fig. 9A, at 62 at 76) on which a float electrode is disposed (Fig. 9A), wherein the float electrode is disposed on a central part in a length direction of the second dielectric layer (Fig. 9A, center from left to right), is spaced apart from both side surfaces of the second dielectric layer (Fig. 9A), and both ends of the float electrode overlap parts of the first and second bottom electrodes (Fig. 9A), wherein the float electrode forms a capacitance with each of the first and second bottom electrodes (Fig. 9A, thru 66/68), wherein the ceramic body comprises a plurality of dummy electrodes (Fig. 9A, 10/11) disposed on and above the second dielectric layer and exposed to both side surfaces of the ceramic body (Fig. 9A), and wherein an interval between the first and second bottom electrodes and the dummy electrode located at a lowermost part or an interval between the dummy electrodes is an interval at which a solder is able to rise along the dummy electrode during soldering of the first and second bottom electrodes onto a substrate (Fig. 9A, solder can be made to rise as higher or as little as you want when placing it so one would be capable or siring the solder only to the location that would teach this limitation). Regarding claim 4, Devoe further discloses that the ceramic body further comprises a plurality of third dielectric layers (Fig. 9A, layer above and below 66/68) on which a dummy electrode is disposed (Fig. 9A, 36/66), and wherein the dummy electrode is exposed to both side surfaces of the ceramic body (Fig. 9A). Regarding claim 8, Devoe further discloses that the ceramic body further comprises a third dielectric layer (Fig. 9A, top layer at 65), and wherein the dummy electrodes are formed on both sides of at least one of upper surfaces and lower surfaces of the second dielectric layer and the third dielectric layer (Fig. 9A), are exposed to both side surfaces thereof, and are shaped to face each other (Fig. 9A). Regarding claim 10, Devoe further discloses that dummy electrode parts exposed to the both side surfaces of the ceramic body and the first and second bottom electrodes are connected by plating (Fig. 9A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devoe et al (US 2004/0042156) in view of JEONG et al (US 2020/0105467). Regarding claim 7, Devoe fails to teach the claim limitations. JEONG teaches that an interval in a height direction between the dummy electrodes is 2 μm to 3 μm ([0090]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of JEONG to the invention of Devoe, in order to improve the reliability of the capacitor (JEONG [0008]). Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devoe et al (US 2004/0042156) in view of CHO et al (US 2015/0068792). Regarding claim 9, Devoe fails to teach the claim limitations. CHO teaches that the dummy electrode is formed in one of a straight shape, a “c” shape (Fig. 4B, 123’/124’ have this shape), and a “T” shape. It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of CHO to the invention of Devoe, in order to increase capacitance without allowing for short circuiting (CHO [0009]). Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devoe et al (US 2004/0042156) in view of PARK et al (US 2016/0133384). Regarding claim 12, Devoe fails to teach the claim limitations. PARK teaches that a distance between the dummy electrode located at an uppermost part among the dummy electrodes and the bottom electrode is equal to or less than a half of a height of the ceramic body (Fig. 3, each section of different electrode pairs are less than half the size of the capacitor). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of PARK to the invention of Devoe, in order to allow for multiple capacitor sections in one body (PARK Fig. 2-3). Additional Relevant Prior Art: Oakes et al (US 2009/0040687) teaches relevant art in Fig. 4A. Zuo et al (US 2013/0083044) teaches relevant art in Fig. 12A. AHN et al (US 2013/0321981) teaches relevant art in Fig. 11-18. KIM et al (US 2018/0174757) teaches relevant art in Fig. 5. PARK et al (US 2019/0157004) teaches relevant art in Fig. 1-6. Response to Arguments Applicant's arguments filed 01/14/2026 have been fully considered but they are not persuasive. In response to applicant's argument that Fig. 12A of Devoe fails to teach the claim limitations, the examiner notes that though this is true Fig. 9A of Devoe does teach the new claim limitations as shown above. In response to applicant's argument that the internal electrodes are not exposed at the side surfaces, the examiner notes that the claims require the electrodes exposed at the side surfaces of the ceramic body, which they are as shown in Fig. 9, not that they are uncovered from external electrodes or exposed to the outer side surface of the capacitor as a whole. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., that the external electrodes are directly connect to a circuit board) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Applicant therefore does not provide any persuasive evidence that the limitations as claimed are not taught by the prior art. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

May 18, 2024
Application Filed
Oct 29, 2025
Non-Final Rejection — §102, §103
Jan 14, 2026
Response Filed
Mar 17, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MONOLITHIC MULTILAYERED CERAMIC CAPACITOR
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Patent 12590195
POLYPROPYLENE FILM, POLYPROPYLENE FILM INTEGRATED WITH METAL LAYER, AND FILM CAPACITOR
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Patent 12592339
MULTILAYER CERAMIC CAPACITOR
2y 5m to grant Granted Mar 31, 2026
Patent 12586727
MULTILAYERED CAPACITOR AND METHOD FOR MANUFACTURING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12586718
MULTILAYER CERAMIC ELECTRONIC COMPONENT
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+20.4%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 815 resolved cases by this examiner. Grant probability derived from career allow rate.

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