Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/711,599 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because of the claim mapping below. Claim 1 of Instant Application is broader than Claim 1 of copending Application No. 18/711,599.
Instant Application
Claim 1. A printed wiring board comprising: a first insulating layer having a first main surface and a second main surface opposite to the first main surface; a first wire pattern, a second wire pattern and a first ground pattern disposed on the second main surface and extending along a first direction in a plan view; a second ground pattern disposed on the first main surface; an adhesive layer disposed on the second main surface so as to cover the first wire pattern, the second wire pattern and the first ground pattern; a second insulating layer disposed on the adhesive layer and having a third main surface facing the adhesive layer side and a fourth main surface opposite to the third main surface; a third ground pattern disposed on the fourth main surface; and a first conductor layer, wherein the first ground pattern is located between the first wire pattern and the second wire pattern in a second direction orthogonal to the first direction, and is spaced apart from the first wire pattern and the second wire pattern, a plurality of first through-holes passing through the first insulating layer, the first ground pattern, the second ground pattern, the adhesive layer, and the second insulating layer and the third ground pattern in a thickness direction are formed in the first insulating layer, the first ground pattern, the second ground pattern, the adhesive layer, the second insulating layer, and the third ground pattern, the plurality of first through-holes are spaced apart from each other and arranged to line up along the first direction, the first conductor layer is disposed on an inner wall surface of each of the plurality of first through-holes, and is electrically connected to the first ground pattern, the second ground pattern and the third ground pattern, and a width of each of the plurality of first through-holes in the first direction is greater than a width of each of the plurality of first through-holes in the second direction.
Reference Application 18/711,599
Claim 1. A printed wiring board comprising: a first insulating layer having a first main surface and a second main surface opposite to the first main surface; a first wire pattern, a second wire pattern, and a first ground pattern that are disposed on the second main surface and extend along a first direction in a plan view; a second ground pattern disposed on the first main surface; an adhesive layer disposed on the second main surface so as to cover the first wire pattern, the second wire pattern, and the first ground pattern; a second insulating layer disposed on the adhesive layer and having a third main surface facing the adhesive layer and a fourth main surface opposite to the third main surface; a third ground pattern disposed on the fourth main surface; and a first conductor layer and a second conductor layer, wherein in a second direction orthogonal to the first direction, the first ground pattern is located between the first wire pattern and the second wire pattern, and spaced apart from the first wire pattern and the second wire pattern, in the first insulating layer and the second ground pattern, a plurality of first through-holes passing through the first insulating layer and the second ground pattern in a thickness direction orthogonal to the first direction and the second direction, and overlapping the first ground pattern in a plan view are formed, the plurality of first through-holes are spaced apart from each other and arranged to line up along the first direction, in the adhesive layer, the second insulating layer, and the third ground pattern, a plurality of second through-holes passing through the adhesive layer, the second insulating layer, and the third ground pattern in the thickness direction, and overlapping the first ground pattern in a plan view are formed, the plurality of second through-holes are spaced apart from each other and arranged to line up along the first direction, the first conductor layer is disposed on an inner wall surface of each of the plurality of first through-holes, and electrically connected to the first ground pattern and the second ground pattern, the second conductor layer is disposed on an inner wall surface of each of the plurality of second through-holes, and electrically connected to the first ground pattern and the third ground pattern, and each of the plurality of first through-holes and each of the plurality of second through-holes have a width in the first direction and a width in the second direction, and the width in the first direction is larger than the width in the second direction.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takano (US2020/0015351 A1) in view of Huang et al. (US 2018/0108965 A1) hereinafter Huang.
Regarding claim 1, Takano discloses, in Fig.16-17, a printed wiring board comprising: a first insulating layer (1020) having a first main surface (top surface of 1020) and a second main surface (bottom surface of 1020) opposite to the first main surface; a first wire pattern (2100), a second wire pattern (2200) and a first ground pattern (3200) disposed on the second main surface and extending along a first direction in a plan view (2100,2200 and 3300 extend into the paper) ; a second ground pattern (5000) disposed on the first main surface; an adhesive layer (1030) disposed on the second main surface so as to cover the first wire pattern, the second wire pattern and the first ground pattern (see 1030 cover 2100,2200,2300); a second insulating layer (1010) disposed on the adhesive layer (1030) and having a third main surface (top surface of 1010) facing the adhesive layer side and a fourth main surface (bottom surface of 1010) opposite to the third main surface; a third ground pattern (4000) disposed on the fourth main surface ( bottom surface of 1010); and a first conductor layer (6200), wherein the first ground pattern (3200) is located between the first wire pattern (2100) and the second wire pattern (2200) in a second direction orthogonal to the first direction (left right direction), and is spaced apart from the first wire pattern and the second wire pattern (see Fig.17), a plurality of first through-holes (holes 6200;Fig.16) passing through the first insulating layer, the first ground pattern, the second ground pattern, the adhesive layer, and the second insulating layer and the third ground pattern in a thickness direction(see 6200 passing through 5000,1020,1030,1010,4000) are formed in the first insulating layer, the first ground pattern, the second ground pattern, the adhesive layer, the second insulating layer, and the third ground pattern (see 6200 passing through 5000,1020,1030,1010,4000), the plurality of first through-holes are spaced apart from each other and arranged to line up along the first direction (see plurality of 6200 spaced apart from each other Fig.16), the first conductor layer (conductor in 6200) is disposed on an inner wall surface of each of the plurality of first through-holes (see Fig.17), and is electrically connected to the first ground pattern, the second ground pattern and the third ground pattern ( via conductor in 6200 electrically connects 5000,4000 and 3200).
Takano is silent with respect to a width of each of the plurality of first through-holes in the first direction is greater than a width of each of the plurality of first through-holes in the second direction.
Huang discloses a width of each of the plurality of first through-holes (see length of VA VA; Fig.1) in the first direction is greater than a width of each of the plurality of first through-holes in the second direction (see width of VA; Fig.1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Huang to modify the through holes of Takano in order to improve thermal performance by dissipating more heat.
Regarding claim 2, Takano discloses wherein each of the plurality of first through-holes extends along the first direction in a plan view (see plurality of 6200 in Fig.16).
Claim (s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takano in view of Huang as applied to claim 1 above, and further in view of Jain et al. (US 6133805) hereinafter Jain.
Regarding claim 3, Takano discloses, in Fig.2-4, a second conductor layer (54;Fig.2), wherein a plurality of second through-holes (see 55;Fig.2) passing through the first insulating layer (60;Fig.4), the first ground pattern (35), the second ground pattern (70), the adhesive layer (80), the second insulating layer (10), and the third ground pattern (40) in the thickness direction are formed in the first insulating layer, the first ground pattern, the second ground pattern, the adhesive layer, the second insulating layer, and the third ground pattern (see Fig.4) , a position of each of the plurality of second through-holes (see plurality of 55 in Fig.2) in the first direction is displaced from a position of each of the plurality of first through-holes (see plurality of 54 in Fig.2 ) in the first direction, the second conductor layer (see conductor in 55;Fig.4) is disposed on an inner wall surface of each of the plurality of second through-holes (see inner wall surface of 55) and is electrically connected to the first ground pattern (see 55 electrically connected to 35), the second ground pattern (70) and the third ground pattern (40).
Takano fails to specifically disclose the plurality of second through-holes are spaced apart from each other and arranged to line up along the first direction between a line of the plurality of first through- holes and the second wire pattern and a width of each of the plurality of second through-holes in the first direction is greater than a width of each of the plurality of second through-holes in the second direction.
Huang discloses a width of each of the plurality of first through-holes (see length of VA VA; Fig.1) in the first direction is greater than a width of each of the plurality of first through-holes in the second direction (see width of VA; Fig.1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Huang to modify the plurality of second through holes of Takano in order to improve thermal performance by dissipating more heat.
Jain discloses a plurality of second through-holes (see holes 808 in grounding layer 803;Fig.8) are spaced apart from each other and arranged to line up along the first direction between a line of the plurality of first through- holes (see holes in 805) and the second wire pattern (801;Fig.8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Jian to modify the printed circuit board of Jain in order to improve isolation of signal layers to increase performance.
Regarding claim 4, a modified Takano discloses wherein each of the plurality of first through-holes (see plurality of 54) and each of the plurality of second through-holes (see plurality of 55) extend along the first direction in a plan view.
Allowable Subject Matter
Claims 5-6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
Regarding claim 5 The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein each of the plurality of first through-holes and each of the plurality of second through-holes have a first portion extending along the first direction in a plan view, and a second portion connected to a central portion of the first portion in the first direction, in each of the plurality of first through-holes, the second portion extends from the first portion along a direction from the first wire pattern side to the second wire pattern side, and in each of the plurality of second through-holes, the second portion extends from the first portion along a direction from the second wire pattern side to the first wire pattern side" in combination with the remaining limitations of the claim 1 and claim 3.
Regarding claim 5 The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein each of the plurality of first through-holes and each of the plurality of second through-holes have a third portion and a fourth portion extending linearly in a plan view, one end of the third portion and one end of the fourth portion are connected to each other, the one end of the third portion is located on one side in the first direction relative to the other end of the third portion, the one end of the fourth portion is located on the other side in the first direction relative to the other end of the fourth portion, in each of the plurality of first through-holes, the other end of the third portion and the other end of the fourth portion are located on the second wire pattern side relative to the one end of the third portion and the one end of the fourth portion, respectively, and in each of the plurality of second through-holes, the other end of the third portion and the other end of the fourth portion are located on the first wire pattern side relative to the one end of the third portion and the one end of the fourth portion, respectively" in combination with the remaining limitations of the claim 1 and claim 3.
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2848