Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9, 18, 21 and 22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Delshadpour (US 12568054 B2), hereafter referred to as “Delshadpour”.
Regarding claim 1, in the embodiments of Figs. 1-3, Delshadpour discloses:
a plurality of amplifier circuits connected in series (Fig. 1, input buffers 108 and 112),
each of the plurality of amplifier circuits having a 0 dB frequency at which magnitude of a normalized transfer function normalized at a low frequency gain becomes 1 at a frequency other than a direct current (a buffer amplifier, also known in the art as a voltage follower or unity-gain amplifier, inherently has a low frequency gain of 1, also known in the art to be equivalent to 0 dB).
Regarding claims 18, 21, and 22, in the embodiment of Figs. 1-3, 6 and 7, Delshadpour discloses:
A multi-stage amplifier (Fig. 1), comprising:
a plurality of amplifier circuits (Fig. 1, input buffers 108 and 112) connected in series, each of the plurality of amplifier circuits having a o dB frequency at which magnitude of a normalized transfer function normalized at a low frequency gain becomes 1 at a frequency other than a direct current (a buffer amplifier, also known in the art as a voltage follower or unity-gain amplifier, inherently has a low frequency gain of 1, also known in the art to be equivalent to 0 dB), wherein the amplifier circuit in each stage includes a first amplifier circuit and a second amplifier circuit connected at a stage subsequent to the first amplifier circuit (108 and 112 comprise of input buffer circuits shown in Figs. 2, 3, 6 and 7), wherein
a lower frequency among the o dB frequencies of the first amplifier circuit is equal to the 0 dB frequency of the second amplifier circuit, and a product of an extreme value of the magnitude of the normalized transfer function of the first amplifier circuit at the lower frequency and an extreme value of the magnitude of the normalized transfer function of the second amplifier circuit is 1 (a buffer amplifier inherently is designed to have unity gain at DC (0 Hz), the maximum value of the magnitude of the normalized transfer function is 1 (0 db) per claim 22).
wherein the first amplifier circuit includes:
a first amplifier (i.e. the amplifier shown in Fig. 1 or differential amplifiers 612/712, shown in Figs. 6 and 7) configured to amplify a signal input to a signal input terminal;
a first output resistor (Figs. 6 and 7, resistors RS1, respectively) having a first end connected to an output terminal of the amplifier (through current sources IC, respectively); and
a first inductor (capacitor CS may include and inductor LS per column 5 lines 12-17) having a first end connected to a second end of the output resistor (RS1 side connected to capacitor CS would also be connected to inductor LS) and having a second end connected to a signal output terminal (inductor LS would inherently be connected to differential mode output signals Vop-5 and Von-5 and Vop-6 and Von-6 in Figs. 6 and 7) wherein the a first inductor having a first end connected to a second end of the first output resistor, and wherein
the second amplifier circuit includes:
a second amplifier configured to amplify a signal input from the first amplifier circuit (as shown with input buffer 112 in Fig. 1);
a second output resistor having a first end connected to an output terminal of the second amplifier; and
a second inductor having a first end connected to a second end of the second output resistor and having a second end is connected to a signal output terminal (the second input buffer would have the same structure as the above described amplifier circuit as per column 5 lines 43-47).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 10-17, 19, 20, and 23:
the cited prior art of record, Delshadpour (US 12568054 B2), either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “an input capacitance connected between a signal input terminal and ground” and “an output capacitance connected between a second end of the output resistor and ground” per claims 10 and 14,
“a first input capacitance connected between a signal input terminal
and a ground”, “a first output capacitance connected between a second end of the first output resistor and ground”, “a second input capacitance connected between a second end of the first inductor and ground”, and “a second output capacitance connected between the signal output terminal and the ground” per claim 14,
“an input capacitance of another one of the plurality of the amplifier circuits in a following stage connected to the one of the plurality of amplifier circuits in each stage of the multi-stage amplifier is represented by Cnx, Q=(L/Cnx)l/2/Rv, and kc=Co/Cnx, and ranges of Q and kc are expressed by:
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158
975
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” per claim 19, and
“Cnx is a second input capacitance of the second amplifier circuit, I h(D.a2) I is an extreme value of a normalized transfer function of the first amplifier circuit at a lower frequency of the o dB frequency of the first amplifier circuit, Q=(L/Cnx)l/2/Ro, and kc=Co/Cnx, ranges of Q and kc are expressed by:
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204
975
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” per claim 23.
Claims 11-13, 15-17, and 20 are objected to as they are dependent on claims 10, 14, and 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Malane Lieng/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
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