DETAILED ACTION
This Office Action is in response to a Non-Final office action, filed on 07/09/2026, on an application filed on 05/21/2014. Claims 1-9 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment and Remarks
Independent claim 6, in Applicant's Claim Amendments (filed on 07/09/2026) has been fully considered and is allowed due to incorporating the limitation of objected claim 6 with the limitations of base method independent claim 5.
The limitations of objective claim 6 defines the following limitations into the method:
“The subsequent step of a surface roughening step, where performing the surface roughening treatment on the surface that is the opposite side to the first surface side in the metal layer and have an arithmetic average roughness (Ra) no lower than 1.0 µm and no higher than 2.0 µm”.
Independent claim 8, in Applicant's Claim Amendments (filed on 07/09/2026) has been fully considered and is allowed due to incorporating the limitation of objected claim 8 with the limitations of base method independent claim 5.
The limitations of objective claim 8 defines the following limitations into the method:
“The second insulating substrate is formed of a photosensitive resin varnish, and the first stacking step includes the step of printing the photosensitive resin varnish so as to cover the metal layer from the first surface side, and have the step of making the metal layer and the photosensitive resin varnish coplanar with each other”.
However, Applicant's Amendment and Argument/Remarks (filed 08/20/2025) with respect to the 102 rejections of independent claims 1 and 5 are moot. Applicant’s argument indicates that the reference of Akio does not disclose the limitation of “metal layer… has a pattern and including a copper single layer structure”. However, Akio discloses, as REASONABLY INTERPRETED by ¶[0019], “that pattern of metal layer 12a may include a copper single layer structure, where the first wiring patterns 12a and 12b are made of a Cu metal structure”. The reasonably interpreted of ¶[0019] is RATIONAL by ¶[0033-0034], that “wiring patterns 22a and 22b that are formed by semi-additive/fully additive/ or subtractive method”. Therefore, the method of forming the “pattern of metal layer 12a” is DIFFERENT from the method of forming the “wiring patterns 22a and 22b”.
As for as the limitation of “via…and including a conductive paste”, the reference of Akio with be augmented by the reference of Kim in a 103 obvious rejection instead of just Akio in a 102 rejection.
In addition, MPEP § 2144 indicates “The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law”.
Consequently, in view NEW amended limitations in independent claims 1 and 5, a Final will ensued.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Akio (JP2005051113A and Akio hereinafter), in view of Kim et al. (US20130133926A1 and Kim hereinafter).
Regarding claim 1, Akio discloses a circuit board comprising: in that a plurality of laminates which include a first insulating substrate (item 1 of Fig. 4 & items 18a, 28a, 18b, 28b, 16a of Figs. 3b-5 and ¶[0029_0031_0036_0039_0041 & 0043] from Espacenet Translation shows and indicates circuit board 1 {wiring board 1, indicated in ¶[0039_0041 & 0043]} comprising in that the plurality of laminates 28a_18a & 28b_18b {laminates form by first interlayer insulating films 18a and 18b and second interlayer insulating film 28a and 28b, indicated in ¶[0036]}; where laminate 28a_18a include first insulating substrate 16a {second resin films 16a, indicated in ¶[0029 & 0031]}), a metal layer formed on a first surface of the first insulating substrate to have a pattern and including a copper single layer structure (items 12a, 16a, 14a, 22a, 22b of Figs. 3b-5 and ¶[0019_0033-0034_0025-0027 & 0029-0031] from Espacenet Translation shows and indicates metal layer 12a {first wiring patterns 12a, indicated in ¶[0019_0025-0027 & 0029-0031]} formed on first surface 16a_14a {contact surfaces between second resin film 16a and first resin films 14a} of first insulating substrate 16a to have pattern of metal layer 12a that includes a copper single layer structure {reasonably interpreted by ¶[0019] where the first wiring patterns 12a and 12b are made of a Cu full metal structure, as oppose to second wiring patterns 22a and 22b that are formed by semi-additive/fully additive/ or subtractive method, indicated in ¶[0033-0034]}); a second insulating substrate stacked in a place of the first surface where the metal layer is not disposed so as to have a same thickness as the metal layer (item 14a of Figs. 3b-5 and ¶[0026-0027_0029 & 0031] from Espacenet Translation shows and indicates second insulating substrate 14a {first resin films 14a} stacked in the place of first surface 16a_14a where metal layer 12a is not disposed so as to have the same thickness as metal layer 12a), a third insulating substrate stacked on a second surface at an opposite side to the first surface of the first insulating substrate (item 24a of Figs. 3b-5 and ¶[0036] from Espacenet Translation shows and indicates third insulating substrate 24a {first resin film 24a} stacked on second surface 16a_24a {contact surfaces between second resin film 16a and first resin film 24a} at the opposite side to first surface 16a_14a of first insulating substrate 16a), and a via formed from a surface at an opposite side to first insulating substrate side of the third insulating substrate until the via reaches the metal layer, is stacked (item 16x of Fig. 3a & Figs. 3b-5 and ¶[0031-0033] from Espacenet Translation shows and indicates via 16x {Cu films are formed on the inner surfaces of the first via hole 16x, where first via holes 16x are connected to the first wiring patterns 12a} formed from the surface at the opposite side to first insulating substrate 16a side of third insulating substrate 24a until via 16x reaches metal layer 12a, is stacked).
Akio discloses the claimed invention except to disclose a via including a conductive paste.
Kim discloses a via including a conductive paste (item 12 of Fig. 2F & items 13, 15, 16 of Fig. 4F & item 33 of Fig. 5 and ¶[0049_0056 & 0063] shows and indicated via 33 including conductive paste 16 {metal seed layer 13 on metal pattern plating layer 15, and where the filling of the conduction hole 12, in which the metal pattern plating layer 15 is formed, is conductive metal paste 16}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a via including a conductive paste into the structure of Akio. One would have been motivated in the circuit board of Akio and have the via include the conductive paste, in order to fill the conduction hole with a conductive metal paste that is an optional after the metal seed layer and metal pattern plating forms the inner wall of the via hole conductor known to one of ordinary skill in the art, as indicated by Kim in ¶[0049] and shown by Kim transitioning from Fig. 2G to Figs. 4F-5, in the circuit board of Akio.
Regarding claim 9, modified Akio disclose an electronic device comprising: the circuit board; and an electronic component (Akio: item 60 of Fig. 5 and ¶[0041 & 0043] from Espacenet Translation shows and indicates where circuit board 1 is comprised of electronic component 60 {semiconductor element 60}).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Akio in view of Kim, as detailed in the rejection of claim 1 above, in view of Tsukamoto (US20170372997A1 and Tsukamoto hereinafter).
Regarding claim 2, modified Akio disclose a circuit board, wherein the via are formed so as to decrease in cross-sectional area in a direction from the third insulating substrate toward the second insulating substrate (Akio: Fig. 3a & Figs. 3b-5 and ¶[0025-0027_0029 & 0031-0033] from Espacenet Translation shows that via 16x are formed so as to decrease in cross-sectional area in a direction from third insulating substrate 24a toward second insulating substrate 14a).
However, Akio and Kim do not disclose wherein the metal layer and the via are formed so as to decrease in cross-sectional area in a direction from the third insulating substrate toward the second insulating substrate.
Tsukamoto disclose wherein the metal layer and the via are formed so as to decrease in cross-sectional area in a direction from the third insulating substrate toward the second insulating substrate (items 22, 15, 14, 17 of Fig. 7B and ¶[0028-0030_0082 & 0087] shows and indicates where metal layer 22 {wirings 22, indicated in ¶[0030 & 0082]} and via 15 {wiring layer 15, indicated in ¶[0028-0030 & 0082]} are formed so as to decrease in cross-sectional area in a direction from third insulating substrate 14 {insulating layer 14, indicated in ¶[0028-0030 & 0082]} toward second insulating substrate 17 {insulating layer 17, indicated in ¶[0028 & 0087]}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the metal layer and the via are formed so as to decrease in cross-sectional area in a direction from the third insulating substrate toward the second insulating substrate into the structure of modified Akio. One would have been motivated in the circuit board of modified Akio and have the metal layer and the via be formed so as to decrease in cross-sectional area in a direction from the third insulating substrate toward the second insulating substrate, in order to designed a board with miniaturization and densification of wirings of wiring substrates so as to improve connection reliability, as indicated by Tsukamoto in ¶[0005-0007], in the circuit board of modified Akio.
In addition, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the metal layer and the via be formed so as to decrease in cross-sectional area in a direction from the third insulating substrate toward the second insulating substrate, as shown by Tsukamoto. Further, the applicant has not presented an explanation or indicated in the specifications that any particular shape or form of the metal layer be comprised of a shape that decrease in cross-sectional area in a particular direction that a person of ordinary skill in the art would find obvious in forming the metal layer. Therefore, a change in shape or form is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1976).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Akio in view of Kim, as detailed in the rejection of claim 1 above, in view of Kimura et al. (JP2005136007A and Kimura hereinafter).
Regarding claim 3, modified Akio disclose a circuit board, wherein the second insulating substrate is formed of one of a resin film (Akio: Figs. 3b-5 and ¶[0026-0027_0029 & 0031] from Espacenet Translation shows and indicates second insulating substrate 14a is formed of a resin films).
However, Akio and Kim do not disclose wherein the second insulating substrate is formed of a photosensitive resin film.
Kimura disclose wherein the second insulating substrate is formed of a photosensitive resin film (item 2a of Fig. 3c & item 3a of Fig. 3d & items 10, A’1, A’1 of Fig. 5b and ¶[0021-0024_0031-0032_0045-0047 & 0053] from Espacenet Translation shows and indicates where second insulating substrate A’1 {composite sheet A'1/lower ceramic photosensitive insulating layer 2a} is formed of a photosensitive resin film; and where laminate of Fig. 5b include first insulating substrate A’2 {composite sheet A'2/upper ceramic photosensitive insulating layer 2a}, metal layer 3a-lower {lower wiring layer 3a} formed on the first surface of first insulating substrate A’2, second insulating substrate A’1 stacked in a place of the first surface where metal layer 3a-lower is not disposed so as to have the same thickness as metal layer 3a-lower, third insulating substrate 10-upper {upper carrier film/resin film 10} stacked on the second surface at the opposite side to the first surface of first insulating substrate A’2, and via 3a-upper {upper wiring layer 3a} formed from the surface at the opposite side to first insulating substrate A’2 side of third insulating substrate 10-upper until via 3a-upper reaches metal layer 3a-lower, is stacked).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the second insulating substrate is formed of a photosensitive resin film into the structure of modified Akio. One would have been motivated in the circuit board of modified Akio and have the second insulating substrate be formed of a photosensitive resin film, in order to provide a composite sheet simultaneously satisfying thinning of an insulating layer and the thickening of a wiring layer, while easily forming a fine wiring, as indicated by Kimura in the abstract, in the circuit board of modified Akio.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Akio in view of Kim, as detailed in the rejection of claim 1 above, in view of Hida (JP2013062293A and Hida hereinafter).
Regarding claim 4, modified Akio disclose a circuit board, wherein a surface at the second surface side in the metal layer (Akio: Figs. 3b-5 and ¶[0025-0027 & 0029-0031] from Espacenet Translation shows and indicates the surface at second surface 16a_24a of first insulating substrate 16a side in metal layer 12a).
Hida disclose wherein the metal layer is subjected to a surface roughening treatment so as to have an arithmetic average roughness (Ra) no lower than 1.0 µm and no higher than 2.0 µm (items 16, 17, 28, 29 of Fig. 1 and ¶[0044 & 0049] from Espacenet Translation shows and indicates where metal layers 28 & 29 { surface roughening treatment may be performed on the inner wiring patterns 28 and 29} is subjected to a surface roughening treatment so as to have an arithmetic average roughness (Ra) no lower than 1.0 µm and no higher than 2.0 µm {roughen the entire surface of the resin insulating layers 16, 17 to a surface roughness Ra of about 2 μm; where, it is construed then that wiring patterns 28 and 29 will be subject to have an arithmetic average roughness (Ra) no lower than 1.0 µm and no higher than 2.0 µm}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the metal layer is subjected to a surface roughening treatment so as to have an arithmetic average roughness (Ra) no lower than 1.0 µm and no higher than 2.0 µm into the structure of modified Akio. One would have been motivated in the circuit board of modified Akio and have the metal layer be subjected to a surface roughening treatment so as to have an arithmetic average roughness (Ra) no lower than 1.0 µm and no higher than 2.0 µm, in order to improve the adhesion between the metal layers/inner wiring patterns and the resin insulating layers, as indicated by Hida in ¶[0049], in the circuit board of modified Akio.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Akio in view of Kim.
Regarding claim 5, Akio discloses a method for manufacturing a circuit board comprising: a first step of forming a laminate with a metal layer formation step of forming a metal layer on a first surface of a first insulating substrate to have a pattern, the metal layer including a copper single layer structure (item 1 of Fig. 4 & items 18a, 28a,16a, 12a, 22a, 22b of Figs. 3b-5 and ¶[0019_0033-0034_0025-0031_0036_0039_0041 & 0043] from Espacenet Translation shows and indicates the method for manufacturing circuit board 1 {wiring board 1, indicated in ¶[0039_0041 & 0043]} comprising the first step of forming laminate 28a_18a {laminate form by first interlayer insulating film 18a and second interlayer insulating film 28a, indicated in ¶[0036]}; where laminate 28a_18a is formed with the metal layer formation step of forming metal layer 12a {first wiring patterns 12a, indicated in ¶[0019_0025-0027 & 0029-0031]} on first surface 16a_14a {contact surfaces between second resin film 16a and first resin films 14a} of first insulating substrate 16a {second resin films 16a, indicated in ¶[0029 & 0031]} to have a pattern of metal layer 12a that includes a copper single layer structure {reasonably interpreted by ¶[0019] where the first wiring patterns 12a and 12b are made of a Cu full metal structure, as oppose to second wiring patterns 22a and 22b that are formed by semi-additive/fully additive/ or subtractive method, indicated in ¶[0033-0034]}); a first stacking step, as a subsequent step, of stacking a second insulating substrate to have a same thickness as the metal layer in a place of the first surface where the metal layer is not disposed (item 14a of Figs. 3b-5 and ¶[0026-0027_0029 & 0031] from Espacenet Translation is understood to show and indicate where the first stacking step, as the subsequent step, of stacking second insulating substrate 14a {first resin films 14a} to have the same thickness as metal layer 12a in a place of first surface 16a_14a where metal layer 12a is not disposed), to expose a surface of the metal layer, a second stacking step, as a subsequent step, of stacking a third insulating substrate which is uncured and a resin film in this order on a second surface at an opposite side to the first surface of the first insulating substrate (item 24a of Figs. 3b-5 & Fig. 1 and ¶[0026-0027_0029_0031 & 0036] from Espacenet Translation is understood to show and indicate where to expose the surface of metal layer 12a {as shown in Fig. 1}, the second stacking step, as the subsequent step, of stacking third insulating substrate 24a {first resin film 24a}, which is understood to be uncured, and the resin film in this order on second surface 16a_24a {contact surfaces between second resin film 16a and first resin film 24a} at the opposite side to first surface 16a_14a of first insulating substrate 16a), a via formation step, as a subsequent step, of forming a via hole from a surface at an opposite side to the first insulating substrate side of the resin film until the via reaches the metal layer (item 16x of Fig. 3a & Figs. 3b-5 and ¶[0031-0033] from Espacenet Translation is understood to show and indicate where the via formation step, as a subsequent step, of forming via hole 16x {Cu films are formed on the inner surfaces of the first via hole 16x, where first via holes 16x are connected to the first wiring patterns 12a} from the surface at the opposite side to first insulating substrate 16a side of the resin film until via 16x reaches metal layer 12a), and a separation step, as a subsequent step, of separating the resin film; and a second step of stacking a plurality of the laminates (Figs. 1-5 and ¶[0015-0041] from Espacenet Translation is interpreted to show and indicate where the separation step, as the subsequent step, of separating the resin film; and where the second step of stacking the plurality of laminates 28a_18a & 28b_18b {laminates form by first interlayer insulating films 18a and 18b and second interlayer insulating film 28a and 28b, indicated in ¶[0036]}).
Akio discloses the claimed method except to disclose a via including a conductive paste.
Kim discloses a via including a conductive paste (item 12 of Fig. 2F & items 13, 15, 16 of Fig. 4F & item 33 of Fig. 5 and ¶[0049_0056 & 0063] shows and indicated via 33 including conductive paste 16 {metal seed layer 13 on metal pattern plating layer 15, and where the filling of the conduction hole 12, in which the metal pattern plating layer 15 is formed, is conductive metal paste 16}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a via including a conductive paste into the method of Akio. One would have been motivated in the method for manufacturing a circuit board of Akio and have the via include the conductive paste, in order to for the method to fill the conduction hole with a conductive metal paste that is an optional after the metal seed layer and metal pattern plating forms the inner wall of the via hole conductor known to one of ordinary skill in the art, as indicated by Kim in ¶[0049] and shown by Kim transitioning from Fig. 2G to Figs. 4F-5, in the method for manufacturing a circuit board of Akio.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Akio in view of Kim, as detailed in the rejection of claim 5 above, in view of Kimura.
Regarding claim 7, modified Akio disclose a method for manufacturing the circuit board, wherein the second insulating substrate is formed of a resin film, and the first stacking step includes a step of attaching the resin film so as to cover the metal layer from the first surface side, and a step of making the metal layer and the resin film coplanar with each other (Akio: Figs. 1-5 and ¶[0026-0027_0029 & 0031] from Espacenet Translation is interpreted to show and indicate where second insulating substrate 14a is formed of a resin films; and where it is understood that the first stacking step includes a step of attaching the resin film so as to cover metal layer 12a from t first surface 16a_14a of first insulating substrate 16a side, and a step of making metal layer 12a and the resin film coplanar with each other).
However, Akio and Kim do not disclose in the method wherein the second insulating substrate is formed of a photosensitive resin film.
Kimura disclose wherein the second insulating substrate is formed of a photosensitive resin film (item 2a of Fig. 3c & item 3a of Fig. 3d & items 10, A’1, A’1 of Fig. 5b and ¶[0021-0024_0031-0032_0045-0047 & 0053] from Espacenet Translation shows and indicates where second insulating substrate A’1 {composite sheet A'1/lower ceramic photosensitive insulating layer 2a} is formed of a photosensitive resin film; and where laminate of Fig. 5b include first insulating substrate A’2 {composite sheet A'2/upper ceramic photosensitive insulating layer 2a}, metal layer 3a-lower {lower wiring layer 3a} formed on the first surface of first insulating substrate A’2, second insulating substrate A’1 stacked in a place of the first surface where metal layer 3a-lower is not disposed so as to have the same thickness as metal layer 3a-lower, third insulating substrate 10-upper {upper carrier film/resin film 10} stacked on the second surface at the opposite side to the first surface of first insulating substrate A’2, and via 3a-upper {upper wiring layer 3a} formed from the surface at the opposite side to first insulating substrate A’2 side of third insulating substrate 10-upper until via 3a-upper reaches metal layer 3a-lower, is stacked).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the second insulating substrate is formed of a photosensitive resin film into the method of modified Akio. One would have been motivated in the method for manufacturing the circuit board of modified Akio and have the second insulating substrate be formed of a photosensitive resin film, in order to provide in the method a composite sheet simultaneously satisfying thinning of an insulating layer and the thickening of a wiring layer, while easily forming a fine wiring, as indicated by Kimura in the abstract, in the method for manufacturing the circuit board of modified Akio.
Allowable Subject Matter
Allowable Subject Matter
Claims 6 and 8 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 6, the prior art taken either singularity or in combination fails to anticipate or fairly suggest the limitations of the independent claim, in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper. The prior art fails to teach a combination of limitations of a method for manufacturing the circuit board comprising: …a surface roughening step, as a subsequent step, of performing a surface roughening treatment on a surface at an opposite side to the first surface side in the metal layer to have an arithmetic average roughness (Ra) no lower than 1.0 µm and no higher than 2.0 µm…, as recited in combination in independent claim 6. After careful review of the specification and the claim in the application and a search of the prior art, considering the claim as a whole, the aforementioned recited limitations in combination in independent claim 6, it is believed to render the claim individually patentable over the prior art of record.
Regarding independent claim 8, the prior art taken either singularity or in combination fails to anticipate or fairly suggest the limitations of the independent claim, in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper. The prior art fails to teach a combination of limitations of a method for manufacturing the circuit board comprising: …wherein the second insulating substrate is formed of a photosensitive resin varnish, and the first stacking step includes a step of printing the photosensitive resin varnish so as to cover the metal layer from the first surface side, and a step of making the metal layer and the photosensitive resin varnish coplanar with each other…, as recited in combination in independent claim 8. After careful review of the specification and the claim in the application and a search of the prior art, considering the claim as a whole, the aforementioned recited limitations in combination in independent claim 8, it is believed to render the claim individually patentable over the prior art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
