Prosecution Insights
Last updated: April 19, 2026
Application No. 18/712,775

INFORMATION PROCESSING DEVICE, AND METHOD FOR CONTROLLING INFORMATION PROCESSING DEVICE

Final Rejection §103
Filed
May 23, 2024
Examiner
HUYNH, KIM T
Art Unit
2184
Tech Center
2100 — Computer Architecture & Software
Assignee
NEC Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
91%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
580 granted / 703 resolved
+27.5% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
24 currently pending
Career history
727
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
47.5%
+7.5% vs TC avg
§102
37.1%
-2.9% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 703 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Interpretation 1. The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “configured to” in claims 1-4. Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof. If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function. Claim Rejections - 35 USC § 103 2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 3. Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al. (Pub. No. US2009/0276551) in view of Shao (Pub. No. US20210216485) As per claims 1 and 4, Brown discloses an information processing device (fig. 12, a system) comprising: a central processing unit (fig.4, host cpu set 410); and a host bus adapter (fig.12, I/O adapter 1220) in which input/output (I/O) devices (fig.4, PCIe endpoints 470, 480, 490) conforming to a PCI Express standard (paragraph 90, lines 3-4, not limited to PCIe and other communication protocols and standards may be utilized) are connected to a fabric (fig. 12, a PCIe fabric 1210), wherein the host bus adapter(fig.12, I/O adapter 1220) is an input/output interface of the PCI Express standard (paragraph 90, lines 2-4, the SR-PCIM 1244 communicate with a IOV enabled I/O adapter 1220 via a communication fabric 1210, which in the depicted example is a PCIe fabric) is configured to communicate with an input/output unit (IOU) comprising at least one of the I/O devices by a fabric communication function, and the host bus adapter includes a functional unit (fig.12, physical function 1280) including a plurality of functions (fig. 12, virtual functions (VFs) 1290-1296) conforming to the PCI Express standard, and a mapping table (paragraph 80, line 5, protection table) in which the functions of the functional unit and external I/O devices connected to the fabric are mapped in association with each other. (paragraph 80, lines 5-6, host system 2 1020 may use a memory address translation and protection table (not shown) to map the PCIe memory addresses seen by host system 1 1010 into host system 2 real memory addresses.) Brown discloses all the limitations as the above but does not explicitly disclose the mapping table comprises correspondence entries between function identifiers of the plurality of functions and IOU identifiers of IOUs to which the external I/O devices are connected, and the host bus adapter comprises packet routing functionality configured to determine destination IOUs based on the correspondence entries in the mapping table. However, Shao discloses this. (paragraphs 30-31, a device's functions connected to PCIe fabric or extended fabric mapped to their respective fabrics' own dedicated 256 MB of configuration space. Further, any MMIO transactions in address spaces 208 or 210 may be treated as PCIe configuration access transactions for either PCIe host fabric 100 or extended fabric 118, respectively, receive a memory mapped input/output (MMIO) request for configuration access to an endpoint of the extended PCIe fabric, wherein a destination address of the MMIO request belongs to configuration space of the extended PCIe fabric; generate a configuration request carrying a bus number/device number/function number (BDF) associated with the destination address of the MMIO request.) It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Shao with the teaching of Brown so as for allowing the CPU to interact with devices directly, low-latency communication so as to yield the predicatable result so as to control efficiently, thus enhance the system performance. As per claim 2, Brown discloses wherein the IOU comprises at least one of the I/O devices (fig.4, endpoint 410) that comprises a virtual root port (fig.4, PCI root complex 440). As per claim 3, Brown discloses wherein the virtual root port comprises a routing table(paragraph 80, line 5, protection table), and the virtual root port transfers a packet received via the fabric communication function (paragraph 40, lines 7-8, to perform direct I/O operations greatly increases the speed at which I/O operations may be performed, but requires that the PCIe endpoints 470-490 support I/O virtualization) to a corresponding one of the I/O devices based on the routing table. (paragraph 29, lines 3-4, implemented in any I/O fabric that supports I/O virtualization within the I/O adapters.) Response to Amendment 4. Applicant's amendment filed on 11/26/2026 have been fully considered but are moot in view of the new ground(s) of rejection. 5. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Freimuth et al. [US Patent Pub. No US20200153592] discloses he computer-implemented method creates a set of virtual function path authorization tables, and receives a request from a requester to provide requested data from a virtual function wherein the virtual function is performed by a single root or a multi-root peripheral component interconnect device. Conclusion 6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Contact Information 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV]. The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K. T. H./ Examiner, Art Unit 2184 /HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Read full office action

Prosecution Timeline

May 23, 2024
Application Filed
Aug 23, 2025
Non-Final Rejection — §103
Nov 26, 2025
Response Filed
Mar 17, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
91%
With Interview (+8.2%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 703 resolved cases by this examiner. Grant probability derived from career allow rate.

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