CTNF 18/713,091 CTNF 93884 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 05/23/2024 and 08/05/2025 was filed before the mailing of this action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Status of the Claims Claims 1-12 are canceled. Claims 13-32 have been added as new claims and are pending. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 13-32 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e. an abstract idea) without significantly more. Claims 13-21 recite a method (i.e. process), claims 22-30 recite a processor (i.e. machine) and claims 31 and 32 recite a system (i.e. machine). Therefore claims 13-32 fall within one of the four statutory categories of invention. Independent claims 13, 22, and 31 recite the limitations of in response to receiving an input message: accessing a multicast pattern comprising at least one set of pattern elements, determining, for each pattern element in the at least one set of pattern elements, [a target processor component of the plurality of processor components] and a target memory location based on a mapping applied for the pattern element, the target memory location being one of the plurality of memory locations associated with the [target processor component], and the [target processor component] being different for each pattern element in the set of pattern elements, and multicasting respective target instructions to the [target processor components], the respective target instruction of each of the [target processor components] identifying the target memory location associated with the [target processor component]; updating a state value stored at the target memory location identified by the respective target instruction received by the [target processor component]; and selectively providing one or more output messages related to one or more of the updated state values. The invention and claims are drawn towards a method of operating a message-based processor based on multicast patterns, distributing target instructions to processors to balance computational load. The claim limitations correspond to mathematical concepts (mathematical relationships, mathematical formulas or equations, mathematical calculations) as evidenced by the limitations detailing accessing multicast pattern comprising at least one set of pattern elements, determining for each pattern element in the at least one set of pattern elements, a target memory location based on a mapping applied for the pattern element, updating the a state value stored at the target memory location. The limitations directly correspond to mathematical functions (see Specification “the input message may convey an opcode OPC and an operand value OPV, and a pattern element may provide a pattern value PV, in which case the target instruction instructs the target module to update the state value SV with an operation specified by the opcode OPC and the product of the operand value OPV and the pattern value PV, i.e. SV<- fopc (SV,OPV*PV) Alternatively, the function specified by the opcode OPC may be a ternary function such that: SV<- fop (SV,OPV,PV)). The claims also correspond to mental processes (observation, evaluation, judgment, opinion) since the claim limitations appear to be mathematical functions being implemented vis generic computers, in a computer environment, and/or using a computer as a tool to perform the mathematical equation functions. The claims recite an abstract idea. Note: the features or elements in brackets in the above Step 2A Prong One section are inserted for reading clarity, but are analyzed as “additional elements” under Step 2A Prong Two and Step 2B below. The judicial exception is not integrated into a practical application simply because the claims recite the additional elements of: a message-based processor comprising a plurality of processor components, a target processor component, memory of the message-based processor (claim 22), and also a second message-based processor comprising memory (clam 31). The additional elements are computer components recited at a high-level of generality performing the above-mentioned limitations. The combination of the additional elements are no more than mere instructions to apply the judicial exception using a generic computer. Accordingly, in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than mere instructions to apply the exception using a generic computer. Mere instructions to apply an exception using a generic computer cannot provide an inventive concept. Thus, when viewed as an ordered combination, nothing in the claims add significantly more (i.e. an inventive concept) to the abstract idea. The claims are not patent eligible. Dependent claim 23 recites the limitation of a [multicast unit] to multicast the respective target instructions to the [target processor components]. The claim is further directed to the judicial exception analyzed above, and recites the additional elements of a multicast unit and the target processors. The additional elements amount to “apply it” or merely using a computer as a tool to implement the abstract idea. Accordingly, in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Further, when viewed as an ordered combination, nothing in the claim adds significantly more (i.e. an inventive concept) to the abstract idea. The claim is not patent eligible. Dependent claim 24 recites the limitation that each of the [target processor components] has a [dedicated output message generator]. The claim is further directed to the judicial exception analyzed above, and recites the additional elements of the target processor components and a dedicated output message generator. The additional elements amount to “apply it” or merely using a computer as a tool to implement the abstract idea. Accordingly, in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Further, when viewed as an ordered combination, nothing in the claim adds significantly more (i.e. an inventive concept) to the abstract idea. The claim is not patent eligible. Dependent claim 25 recites the limitation of an [output message generator] that is shared between at least two of the [target processor components]. The claim is further directed to the judicial exception analyzed above, and recites the additional elements of the target processor components and an output message generator. The additional elements amount to “apply it” or merely using a computer as a tool to implement the abstract idea. Accordingly, in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Further, when viewed as an ordered combination, nothing in the claim adds significantly more (i.e. an inventive concept) to the abstract idea. The claim is not patent eligible. Dependent claim 27 recites the limitation that each of the [target processor components] has a respective [memory bank] comprising the plurality of memory locations associated with the [target processor component] and storing respective state values. The claim is further directed to the judicial exception analyzed above, and recites the additional elements of the target processor components and a memory bank. The additional elements amount to “apply it” or merely using a computer as a tool to implement the abstract idea. Accordingly, in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Further, when viewed as an ordered combination, nothing in the claim adds significantly more (i.e. an inventive concept) to the abstract idea. The claim is not patent eligible. Dependent claim 32 recites the limitation that the [first message-based processor] provides a [first layer of a neural network] and the [second message-based processor] provides a [second layer of the neural network]. The claim recites the additional elements of the first message-based processor providing a first layer of a neural network and second message-based processor provides a second layer of the neural network. The additional element of the message-based processors providing the neural network layers amount to “apply it” or merely using a computer as a tool to implement the abstract idea. Further, the neural networks amount to generally linking the judicial exception to a particular field of use (message based processing on multicast patterns). Accordingly, in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Further, when viewed as an ordered combination, nothing in the claim adds significantly more (i.e. an inventive concept) to the abstract idea. The claim is not patent eligible. Dependent claims 14-21, 26, and 28-30 recite additional limitations that are further directed to the abstract idea analyzed in the rejected claims above. The claims also recite additional elements that have been analyzed in the rejected claims above. Thus, claims 14-21, 26, and 28-30 are also rejected under 35 U.S.C. 101. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 13, 14, and 16-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steele (US 8,086,554) in view of Burger (2011/0072239) . Claim 13: Steele discloses: A method of operating a message-based processor, the message-based processor comprising a plurality of processor components, each processor component of the plurality of processor components being associated with a plurality of memory locations, and the method comprising: (Steele Col. 7, Ln. 40-49 disclosing pattern matching can be efficiently performed in a multiprocessor environment for any of a variety of applications such as virus detection, deep packet inspection, or regular expression matching, for example. The multiprocessor environment can include a multi-core processor or an interconnected network of processors, such as the tiled multiprocessor architecture described in more detail below. The multiprocessor environment provides interconnected processing engines that can be used to perform pattern matching on an input stream; Col. 7, Ln. 60-62 packets can be stored in and accessed from memory that is dedicated to specific processing engines, or memory that is shared among multiple processing engines) in response to receiving an input message: accessing a multicast pattern comprising at least one set of pattern elements, (Steele Col. 7, Ln. 56-59 disclosing a stream of data packets, each representing an input sequence to be inspected, enters the system over a network interface; Col. 7, Ln. 46-51 disclosing the multiprocessor environment provides interconnected processing engines that can be used to perform pattern matching on an input stream using different sets of patterns, and/or to perform pattern matching on different portions of an input stream using the same sets of patterns; Col. 13, Ln. 25-27 disclosing enable the multiplexers to move data independently onto any output port from any input port, including multicasting an input port to all output ports) determining, for each pattern element in the at least one set of pattern elements, a target processor component of the plurality of processor components and a target memory location based on a mapping applied for the pattern element, (Steele Col. 7, Ln. 46-51 the multiprocessor environment provides interconnected processing engines that can be used to perform pattern matching on an input stream using different sets of patterns, and/or to perform pattern matching on different portions of an input stream using the same sets of patterns; Col. 10, Ln. 25-31 an integrated circuit (or "chip") includes an array of interconnected tiles that are an example of the interconnected processing engines used for pattern matching. Each of the tiles is a functional unit that includes a processor and a switch that forwards data from other tiles to the processor and to switches of other tiles over data paths. The switch is coupled to the processor so that data can be sent to or received from processors of other tiles) Steele in view of Burger discloses: the target memory location being one of the plurality of memory locations associated with the target processor component, and the target processor component being different for each pattern element in the set of pattern elements, and multicasting respective target instructions to the target processor components, Steele discloses determining, for each pattern element in the at least one set of pattern elements, a target processor component of the plurality of processor components and a target memory location based on a mapping applied for the pattern element, but does not appear to explicitly disclose the target memory location being one of the plurality of memory locations associated with the target processor component, and the target processor component being different for each pattern element in the set of pattern elements, and multicasting respective target instructions to the target processor components. Burger suggests or discloses this limitation/concept: (Burger ¶0021 each instruction identifier may be mapped to a particular coordinate in the array of processing tiles; there may be possible target instructions total in a block of this example, each processing tile may receive eight (8) instructions; there may be possible target instructions total in a block of this example, each processing tile may receive eight (8) instructions; see also ¶0051; ¶0058 data multicasting in a distributed processor architecture, which has multiple, interconnected processing tiles. The method can include identifying a plurality of targets that are configured to receive a first message from a source, providing target routing instructions to the first message for each of the targets; ¶0059 apparatus may also include a router configured to read the target routing instructions to determine the location of each of the targets and route the message to each of the targets; ¶0031 specify up to 16 different targets, which number of targets may vary depending on the bit allocation; also different type of operands; ¶0043 encoding a different set of common bits in instruction). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Steele to include the target memory location being one of the plurality of memory locations associated with the target processor component, and the target processor component being different for each pattern element in the set of pattern elements, and multicasting respective target instructions to the target processor components as taught by Burger since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable. the respective target instruction of each of the target processor components identifying the target memory location associated with the target processor component; Steele discloses determining, for each pattern element in the at least one set of pattern elements, a target processor component of the plurality of processor components and a target memory location based on a mapping applied for the pattern element, but does not appear to explicitly disclose the respective target instruction of each of the target processor components identifying the target memory location associated with the target processor component. Burger suggests or discloses this limitation/concept: (Burger ¶0021 each instruction identifier may be mapped to a particular coordinate in the array of processing tiles; there may be possible target instructions total in a block of this example, each processing tile may receive eight (8) instructions; there may be possible target instructions total in a block of this example, each processing tile may receive eight (8) instructions; see also ¶0051). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Steele to include the respective target instruction of each of the target processor components identifying the target memory location associated with the target processor component as taught by Burger since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable. Steele, as modified above, discloses the following limitations: updating, by each of the target processor components, a state value stored at the target memory location identified by the respective target instruction received by the target processor component; and (Steele Col. 9, Ln. 13-19 the states of the FSA and a set of "success transitions" can be represented by a directed graph called a "keyword tree" 20. In this example, the set of patterns to be matched is {HE, SHE, HIS, HERS}. Each node in the tree 20 represents a state associated with a prefix for at least one pattern in the set (or a complete pattern). The edges of the tree 20 represent transitions from one state to another; Col. 20, Ln. 1-10 an approach to encoding the state transition table, the rows in the table, each representing a state transition vector for a respective state, are encoded into state transition objects and concatenated into an array in memory. The components of the state transition vector are "state ID" values that identify a next state. For example, a state ID value that can be used to uniquely identify each state is the starting address of the encoded state transition object for that state in the array. The addresses can be absolute addresses in a memory address) selectively providing one or more output messages related to one or more of the updated state values. (Steele Col. 15, Ln. 46-48 the compiler output includes a program (e.g., a stream of instructions) for the processor of each participating tile; Col. 15, Ln. 57-60 the compiler output includes a program (e.g., stream of instructions) for each tile processor and switch and optional logic-level instructions; Col. 24, Ln. 51-Col. 25, Ln. 1 rule processor module receives messages from the FSA transition module over the dynamic network that each include an FSA identification number, a pointer to identify a stored character sequence (e.g., a packet), a character position number to identify a character within the sequence, and (optionally) a rule list number; these messages are sent only when the FSA transition module transitions to a particular state (e.g., a match state); since a match state can correspond to matching multiple patterns, a data structure can be stored that provides a rule list for each match state of the patterns that are matched when that state is entered. The rule processor module uses the rule list number to index into the data structure to retrieve the appropriate list of rules to execute. For example, some rules can indicate that the rule processor module should send a message to a registered client) Claims 22 and 31: Claims 22 and 21 are directed to a processor and system, respectively. Claims 22 and 31 recite limitations that are parallel in nature as those addressed above for claim 13, which is directed towards a method. Claims 22 and 31 are therefore rejected for the same reasons as set forth above for claim 1. Furthermore, claim 31 recites: (Claim 31): A message-based processing system comprising a plurality of message-based processors, a first message-based processor of the plurality of message-based processors providing output messages as input messages to a second message-based processor of the plurality of message-based processors, and each message-based processor of the plurality of message-based processors comprising at least one memory that stores instructions, the message- based processor being configured by the instructions to perform operations comprising: (Steele Col. 7, Ln. 40-49 disclosing pattern matching can be efficiently performed in a multiprocessor environment for any of a variety of applications such as virus detection, deep packet inspection, or regular expression matching, for example. The multiprocessor environment can include a multi-core processor or an interconnected network of processors, such as the tiled multiprocessor architecture described in more detail below. The multiprocessor environment provides interconnected processing engines that can be used to perform pattern matching on an input stream; Col. 7, Ln. 60-62 packets can be stored in and accessed from memory that is dedicated to specific processing engines, or memory that is shared among multiple processing engines; Col 1, Ln. 63-67 memory accessible by a first set of one or more processing engines and second set of one or more processing engines) Claim 14: The method of claim 13, wherein each pattern element in the at least one set of pattern elements comprises a pattern value, and the method comprises assigning, to each respective target instruction, the pattern value of the pattern element corresponding to the target processor component of the respective target instruction, and wherein the state value of each of the target processor components is updated using the pattern value assigned to the respective target instruction. (Steele Col. 24, Ln. 51-Col. 25, Ln. 1 rule processor module receives messages from the FSA transition module over the dynamic network that each include an FSA identification number, a pointer to identify a stored character sequence (e.g., a packet), a character position number to identify a character within the sequence, and (optionally) a rule list number; these messages are sent only when the FSA transition module transitions to a particular state (e.g., a match state); since a match state can correspond to matching multiple patterns, a data structure can be stored that provides a rule list for each match state of the patterns that are matched when that state is entered. The rule processor module uses the rule list number to index into the data structure to retrieve the appropriate list of rules to execute. For example, some rules can indicate that the rule processor module should send a message to a registered client; Col. 25, Ln. 30-34 one of each pair of double-matched patterns can be filtered out by a common rule processor module or other gathering module that receives potential pattern matches from the pattern matchers) Claim 28 is directed to a processor. Claim 28 recites limitations that are parallel in nature as those addressed above for claim 14, which is directed towards a method. Claim 28 is therefore rejected for the same reasons as set forth above for claim 14. Claim 16: The method of claim 13, wherein the input message comprises a base address, and the method comprises using the base address to determine one or more of the target memory locations. (Steele Col. 11, Ln. 67-Col. 12, Ln. 1 a tile can send a message to any other tile by generating the appropriate address information; Col. 20, Ln. 6-11 a state ID value that can be used to uniquely identify each state is the starting address of the encoded state transition object for that state in the array. The addresses can be absolute addresses in a memory address space, or they can be relative addresses expressed as an offset from the beginning of a file or the array data structure) Claim 29 is directed to a processor. Claim 29 recites limitations that are parallel in nature as those addressed above for claim 16, which is directed towards a method. Claim 29 is therefore rejected for the same reasons as set forth above for claim 16. Claim 17: The method of claim 13, wherein the at least one set of pattern elements is one of a plurality of sets of pattern elements in the multicast pattern, the method further comprising: performing multicasting for each of the plurality of sets of pattern elements. (Steele Col. 7, Ln. 46-51 disclosing multiprocessor environment provides interconnected processing engines that can be used to perform pattern matching on an input stream using different sets of patterns, and/or to perform pattern matching on different portions of an input stream using the same sets of patterns; Col. 13, Ln. 25-27 disclosing enable the multiplexers to move data independently onto any output port from any input port, including multicasting an input port to all output ports) Claim 18: The method of claim 17, wherein each set of pattern elements of the plurality of sets of pattern elements provides a different mapping for determining one or more target memory locations. (Steele Col. 7, Ln. 46-51 disclosing multiprocessor environment provides interconnected processing engines that can be used to perform pattern matching on an input stream using different sets of patterns, and/or to perform pattern matching on different portions of an input stream using the same sets of patterns; Col. 13, Ln. 25-27 disclosing enable the multiplexers to move data independently onto any output port from any input port, including multicasting an input port to all output ports; Col. 8, Ln. 1-3 disclosing memory, with some of the instructions being stored within a dedicated memory cache of the processing engines of the corresponding FSA module; Col. 10, Ln. 66-67 disclosing there can be multiple "tile types" each having different structure and/or functionality; Col. 16, Ln. 19-20 each pattern matcher can run on a different set of one or more tiles in parallel with the other pattern matchers) Claim 19: The method of claim 13, wherein each pattern element in the at least one set of pattern elements comprises at least one of: relative address information specifying a relative address with respect to a preceding or succeeding pattern element in the at least one set of pattern elements; or a relative target processor component indication with respect to a preceding or a succeeding pattern element in the at least one set of pattern elements. (Steele Col. 19, Ln. variety of encoding formats can be used to store data that specifies the transitions of an FSA from any given current state to the appropriate next state for each possible input character that could be received; Col. 20, Ln. 4-11 components of the state transition vector are "state ID" values that identify a next state. For example, a state ID value that can be used to uniquely identify each state is the starting address of the encoded state transition object for that state in the array. The addresses can be absolute addresses in a memory address space, or they can be relative addresses expressed as an offset from the beginning of a file or the array data structure) Claim 20: The method of claim 13, wherein selectively providing the one or more output messages related to one or more of the updated state values comprises: determining that the one or more updated state values satisfy a change threshold; and in response to determining that the one or more updated state values satisfy the change threshold, generating the one or more output messages. (Steele Col. 16, Ln. 12-15 when a pattern matcher retrieves data from a given packet for processing, the pattern matcher can select a predetermined portion of the packet to interpret as a character sequence; Col. 18, Ln. 28-29 in a D FA, from a given current state, each input character is associated with a transition to a single predetermined next state; Col. 21, Ln. 31-34 matching table can be a separate data structure that includes lists of matched patterns associated with respective match states. If a state is not associated with any matched patterns (a "non-match state"), the matching table index can be set to a predetermined "non-match" value (e.g., "-1")) Claim 30 is directed to a processor. Claim 30 recites limitations that are parallel in nature as those addressed above for claim 20, which is directed towards a method. Claim 30 is therefore rejected for the same reasons as set forth above for claim 20. Claim 21: The method of claim 13, further comprising providing a new output message related to a given state value in response to determining that at least one of: a predetermined number of instructions have been processed without issuing the new output message; or a predetermined number of clock cycles has passed without issuing the new output message. (Steele 8, Ln. 52-53 an external computer or processor can act as a host controller. In some implementations, the host controller can then send a message to a console indicating the detected condition; Col. 10, Ln. 25-36 an integrated circuit 100 (or "chip") includes an array 101 of interconnected tiles 102 that are an example of the interconnected processing engines used for pattern matching. Each of the tiles 102 is a functional unit that includes a processor and a switch that forwards data from other tiles to the processor and to switches of other tiles over data paths 104. The switch is coupled to the processor so that data can be sent to or received from processors of other tiles. The integrated circuit 100 includes other on-chip circuitry such as input/output (I/O) interface circuitry to couple data in and out of the circuit 100, and clock distribution circuitry to provide clock signals to the processors of the tiles; Col. 11, Ln. 25-31 he switch 220 includes input buffers 222 for temporarily storing data arriving over incoming wires 104A, and switching circuitry 224 (e.g., a crossbar fabric) for forwarding data to outgoing wires 104B or the processor 200. The input buffering provides pipelined data channels in which data traverses a path 104 from one tile to a neighboring tile in predetermined number of clock cycles (e.g., a single clock cycle); Col. 13, Ln. 24-29 In a given clock cycle, the control module 304A can enable the multiplexers to move data independently onto any output port from any input port, including multicasting an input port to all output ports, as long as two input ports are not connected to the same output port in the same clock cycle.) Claim 23: The message-based processor of claim 22, further comprising a multicast unit to multicast the respective target instructions to the target processor components. (Steele Col. 13, Ln. 24-29 In a given clock cycle, the control module 304A can enable the multiplexers to move data independently onto any output port from any input port, including multicasting an input port to all output ports) Claim 24: The message-based processor of claim 22, wherein each of the target processor components has a dedicated output message generator. (Steele Col. 2, Ln. 20-22 disclosing at least one of the sets of processing engines is dedicated to performing pattern matching for input sequences in packets of a corresponding class; Col. 7, Ln. 67-Col. 8, Ln. 3 "FSA instructions" are initially stored in an external shared memory, with some of the instructions being stored within a dedicated memory cache of the processing engines of the corresponding FSA module) Claim 25: The message-based processor of claim 22, further comprising an output message generator that is shared between at least two of the target processor components. (Steele Col. 15, Ln. 46-48 the compiler output includes a program (e.g., a stream of instructions) for the processor of each participating tile; Col. 15, Ln. 57-60 the compiler output includes a program (e.g., stream of instructions) for each tile processor and switch and optional logic-level instructions) Claim 26: The message-based processor of claim 22, wherein the input message is one of a plurality of input messages, the message-based processor further comprising an input queue to queue one or more of the plurality of input messages. (Col. 2, Ln. 14-16 indication of the work load comprises at least one of a number of input sequences currently being processed and a number of input sequences in an input queue) Claim 27: The message-based processor of claim 22, wherein each of the target processor components has a respective memory bank comprising the plurality of memory locations associated with the target processor component and storing respective state values. (Col. 2, Ln. 27-29 instructions stored in the memory accessible to the first set of processing engines comprise a program corresponding to a finite state automaton; Col 1, Ln. 63-67 memory accessible by a first set of one or more processing engines and second set of one or more processing engines) 07-21-aia AIA Claim (s) 15 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steele (US 8,086,554) in view of Burger (2011/0072239) further in view of GrAI Matter Labs S.A.S. (“GrAI”) (EP 3 716 154 A1) . Claim 15: The method of claim 13, wherein the multicast pattern comprises a convolution pattern. Steele discloses a multicast patter, but does not explicitly disclose that the multicast pattern comprises a convolution pattern. GrAI suggests or discloses this limitation/concept: (GrAI ¶0012 the computation facility may update the neuromorphic elements in the specified set in accordance with a convolution pattern specified at the indicated one or more entries in the pattern memory). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Steele in view of Burger to include the multicast pattern comprises a convolution pattern as taught by GrAI since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable. Claim 32: The message-based processing system of claim 31, wherein the first message- based processor provides a first layer of a neural network and the second message-based processor provides a second layer of the neural network. Steele discloses a first and second message-based processor, but does not explicitly disclose that the first message- based processor provides a first layer of a neural network and the second message-based processor provides a second layer of the neural network. GrAI suggests or discloses this limitation/concept: (GrAI ¶0011 disclosing neural processing and specifying the topology of the neural network formed with the neuromorphic elements). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Steele in view of Burger to include the first message- based processor provides a first layer of a neural network and the second message-based processor provides a second layer of the neural network as taught by GrAI since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIONE N SIMPSON whose telephone number is (571)272-5513. The examiner can normally be reached M-F; 7:30 a.m.-4:30 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sarah Monfeldt can be reached at (571) 270-1833. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DIONE N. SIMPSON Primary Examiner Art Unit 3628 /DIONE N. SIMPSON/Primary Examiner, Art Unit 3629 Application/Control Number: 18/713,091 Page 2 Art Unit: 3629 Application/Control Number: 18/713,091 Page 3 Art Unit: 3629 Application/Control Number: 18/713,091 Page 4 Art Unit: 3629 Application/Control Number: 18/713,091 Page 5 Art Unit: 3629 Application/Control Number: 18/713,091 Page 6 Art Unit: 3629 Application/Control Number: 18/713,091 Page 7 Art Unit: 3629 Application/Control Number: 18/713,091 Page 8 Art Unit: 3629 Application/Control Number: 18/713,091 Page 9 Art Unit: 3629 Application/Control Number: 18/713,091 Page 10 Art Unit: 3629 Application/Control Number: 18/713,091 Page 11 Art Unit: 3629 Application/Control Number: 18/713,091 Page 12 Art Unit: 3629 Application/Control Number: 18/713,091 Page 13 Art Unit: 3629 Application/Control Number: 18/713,091 Page 15 Art Unit: 3629 Application/Control Number: 18/713,091 Page 16 Art Unit: 3629 Application/Control Number: 18/713,091 Page 17 Art Unit: 3629 Application/Control Number: 18/713,091 Page 18 Art Unit: 3629 Application/Control Number: 18/713,091 Page 19 Art Unit: 3629
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