Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/24/2024, 11/14/2024, 01/23/2025, and 02/03/2025 are considered by the examiner.
Drawings
The drawing submitted on 05/24/2024 is considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9, 17, 19, and 21, are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims 1-9, 17, 19, and 21, recites, determining a first cross-correlation coefficient for a left channel signal and a right channel signal of a current frame of a stereo audio signal; and in response to the first cross-correlation coefficient being less than a first threshold, obtaining two decorrelation processed channel signals by using a first decorrelation processing method to decorrelate the current frame of the stereo audio signal, calculating a second cross- correlation coefficient for the two decorrelation processed channel signals, and in response to the first cross-correlation coefficient being less than the second cross-correlation coefficient, determining a flag bit to be a first value, obtaining a coded stream based on the two decorrelation processed channel signals, and writing the flag bit into the coded stream, wherein a value of the first threshold is in a range of (-1, 0), as drafted is a process which is a statutory category of invention.
The steps of determining, obtaining, and calculating, in the limitation of, “determining a first cross-correlation coefficient for a left channel signal and a right channel signal of a current frame of a stereo audio signal; and in response to the first cross-correlation coefficient being less than a first threshold, obtaining two decorrelation processed channel signals by using a first decorrelation processing method to decorrelate the current frame of the stereo audio signal, calculating a second cross- correlation coefficient for the two decorrelation processed channel signals”, requires a mathematical calculation based on mathematical constrained. For example, applicant specification cited in [0047-0049], [0051], and [0062-0063] first cross-correlation coefficient for the left channel signal and the right channel signal based on a formula III and second cross-correlation coefficient based on formula IV. Thus, the limitation recites mathematical concept grouping of abstract ideas.
The steps of obtaining in the limitation of “in response to the first cross-correlation coefficient being less than the second cross-correlation coefficient, determining a flag bit to be a first value, obtaining a coded stream based on the two decorrelation processed channel signals, and writing the flag bit into the coded stream, wherein a value of the first threshold is in a range of (-1, 0)” covers performance of the limitation in the mind.
That is other than reciting, by a coding device (claim 1) or by a processor (claims 17 and 21) or by a interface circuit ( claims 19 and 20), nothing in the claim element precludes the step from practically being performed in the mind. For example, observing and comparing two (first and second) cross-correlation coefficient written in a piece of paper and based on that the observation and determination one is less than other, writing down a coded data of decorrelation processed/convergence channel stream out of an infinite number, along with a randomly and manually assigning or labeling a flag value/bit into the written coded data in that piece of paper. In addition, manually predetermining a threshold range from a set of values (-1, 0). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. When a claim recites multiple abstract ideas that fall in the same or different groupings, examiners should consider the limitations together as a single abstract idea, rather than as a plurality of separate abstract ideas to be analyzed individually. See MPEP 2106.04, subsection II.B. Accordingly, the claim recites an abstract idea.
The judicial exception is not integrated into a practical application. In particular, the claims only recites the additional elements- by a coding device (claim 1), by a processor (claims 17 and 21), by a interface circuit ( claims 19 and 20). These additional elements in all the above claims recited at a high-level of generality (i.e., as a generic processor, device and circuit in [0019-27], [0070] [0189] [0196] [0205] and [0211] processor for running the code instructions to perform the method, the communication device may include one or more processors, the processors may be general processors or specialized processors, decorrelation processing is performed by the coding device, the interface circuit, for receiving code instructions and transmitting the code instructions to the processor, the transceiver circuits, interfaces, or interface circuits described above may be used for code/data reading and writing, or, the transceiver circuits, interfaces, or interface circuits described above may be used for signal transmission or delivery.) such that it amounts no more than mere instructions to apply the exception using a generic computer component.
Thus, the additional limitations amounts to mere instruction to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea. See MPEP 2106.05(f). Accordingly, this additional elements does not integrate the abstract into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claims do not include any other additional elements that are sufficient to amount to
significantly more than the judicial exception. As discussed above with respect to
integration of the abstract idea into a practical application, the additional element
(a coding device, a processor, an interface circuit) to perform the two decorrelation
processed channel signals that amounts to no more than mere instructions to apply the
exception using a generic computer component. The claims do not provide an inventive
concept (significantly more than abstract idea). The claims are ineligible.
Even when considered in combination, these additional elements represents mere instructions to apply an exception and insignificant extra-solution activity (MPEP 2106.05(g)), which cannot provide an inventive concept (significantly more than the abstract idea). The claim is not patent eligible.
With respect to claim 2, which depends on claim 1 and includes all the limitation of claim 1, similarly recites mathematical calculation of “down-mixing processing “ of decorrelation processing and thus falls into the mathematical group of abstract idea, since decorrelation processing with, “down-mixing" constitute mathematical manipulations of data, which are abstract ideas.
With respect to claim 3, which depends on claim 2, recites mathematical calculation using formula which similarly falls under mathematical manipulations of data, which are abstract ideas.
With respect to claim 4, which depends of claim 1 and includes all the limitation of claim 1, similarly recites limitation as, claim 1 except reciting second threshold instead first threshold. Thus, the claim 4 will be similarly directed to an abstract idea as like claim 1.
With respect to claim 5, which depends of claim 4, similarly recites limitation as claim 2, except reciting second decorrelation processing instead first decorrelation processing. Thus, the claim 5, will be similarly directed to an abstract idea as like claim 2.
With respect to claim 6, which depends of claim 5, recites mathematical calculation Mid/Side down-mixing processing, using formula which similarly falls under mathematical manipulations of data, which are abstract ideas.
With respect to claim 7, which depends of claim 4, recites similar limitation with different context/condition for obtaining a coded stream based on the two decorrelation processed channel signals, and writing the flag bit into the coded stream, based on threshold range of (-1, 0) (i.e. performing the mathematical calculation) without placing any limitation on how the coding device operates.
As recited in the rejection of claim 1, the limitations, “obtaining a coded stream," "decorrelation," and "writing a flag bit" constitute mathematical manipulations of data, which are abstract ideas.
With respect to claim 8, which depends of claim 1, and includes all limitation of claim 1, recites mathematical calculation using formula which similarly falls under mathematical manipulations of data, which are abstract ideas.
With respect to claim 9, which depends of claim 4, recites mathematical calculation using formula which similarly falls under mathematical manipulations of data, which are abstract ideas.
The above claims 2-9, do not include any other additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element amounts to no more than mere instructions to apply the exception using a generic computer component.
Even when considered in combination, these additional elements represents mere instructions to apply an exception and insignificant extra-solution activity, which cannot provide an inventive concept (significantly more than the abstract idea). The claim is not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 10, 12, 14, and 17-22, are rejected under 35 U.S.C. 103 as being unpatentable over in view of Wang et al.(US 2020/0176001 A1).
Regarding Claim 1, Wang teaches: A stereo audio signal processing method, performed by a coding device, comprising (0009] A stereo signal in the current frame includes, for example, left and right channel signals in the current frame. [0012] The coding mode of the current frame is one of a plurality of coding modes. For example, the plurality of coding modes may include a correlated-to-anticorrelated signal coding switching mode, an anticorrelated-to-correlated signal coding switching mode, a correlated signal coding mode, and an anticorrelated signal coding mode.): determining a first cross-correlation coefficient (xorr is less than or equal to a first threshold) for a left channel signal and a right channel signal of a current frame of a stereo audio signal ([0029] …determining a signal type of in/out of phase of the stereo signal in the current frame by using the left and right channel signals in the current frame; and determining the initial channel combination scheme for the current frame based on the signal type of in/out of phase of the stereo signal in the current frame and the channel combination scheme for the previous frame. [0032] The determining a signal type of in/out of phase of the stereo signal in the current frame by using the left and right channel signals in the current frame may include: calculating a correlation value xorr between the left and right channel signals in the current frame;); and in response to the first cross-correlation coefficient being less than a first threshold (xorr is less than or equal to a first threshold), obtaining two decorrelation (in/out of phase of the stereo signal in the current frame and the channel combination scheme for the previous frame) processed channel signals by using a first decorrelation (in/out of phase of the stereo signal) processing method to decorrelate the current frame of the stereo audio signal , calculating a second cross-correlation coefficient (xorr is greater than the first threshold) for the two decorrelation processed channel signals([0032] The determining a signal type of in/out of phase of the stereo signal in the current frame by using the left and right channel signals in the current frame may include: calculating a correlation value xorr between the left and right channel signals in the current frame; and when xorr is less than or equal to a first threshold, determining that the signal type of in/out of phase of the stereo signal in the current frame is the near in phase signal; or when xorr is greater than the first threshold, determining that the signal type of in/out of phase of the stereo signal in the current frame is the near out of phase signal. Further, if the signal type of in/out of phase flag of the current frame is used to indicate the signal type of in/out of phase of the stereo signal in the current frame, when it is determined that the signal type of in/out of phase of the stereo signal in the current frame is the near in phase signal, a value of the signal type of in/out of phase flag of the current frame may be set to indicate that the signal type of in/out of phase of the stereo signal in the current frame is the near in phase signal; or when it is determined that the signal type of in/out of phase of the current frame is the near in phase signal, the value of the signal type of in/out of phase flag of the current frame may be set to indicate that the signal type of in/out of phase of the stereo signal in the current frame is the near out of phase signal. [0034] For example, the determining the initial channel combination scheme for the current frame based on the signal type of in/out of phase of the stereo signal in the current frame and the channel combination scheme for the previous frame may include: [0160] For example, the performing initial channel combination scheme decision for the current frame may include: determining a signal type of in/out of phase of the stereo signal in the current frame by using the left and right channel signals in the current frame; and determining the initial channel combination scheme for the current frame based on the signal type of in/out of phase of the stereo signal in the current frame and the channel combination scheme for the previous frame. The signal type of in/out of phase of the stereo signal in the current frame may be a near in phase signal or a near out of phase signal. The signal type of in/out of phase of the stereo signal in the current frame may be indicated by a signal type of in/out of phase flag (for example, the signal type of in/out of phase flag is represented by tmp_SM_flag) of the current frame. For example, when a value of the signal type of in/out of phase flag of the current frame is “1”, it indicates that the signal type of in/out of phase of the stereo signal in the current frame is a near in phase signal; or when the value of the signal type of in/out of phase flag of the current frame is “0”, it indicates that the signal type of in/out of phase of the stereo signal in the current frame is a near out of phase signal; or vice versa.), and in response to the first cross-correlation coefficient being less than the second cross-correlation coefficient, determining a flag (in/out of phase flag) bit (0) to be a first value( [0164] A value range of the first threshold may be, for example, (0.5, 1.0), and the first threshold may be equal to, for example, 0.5, 0.85, 0.75, 0.65, or 0.81. [0165] For example, when a value of a signal type of in/out of phase flag of an audio frame (for example, the previous frame or the current frame) is “0”, it indicates that a signal type of in/out of phase of a stereo signal in the audio frame is the near in phase signal; or when the value of the signal type of in/out of phase flag of the audio frame (for example, the previous frame or the current frame) is “1”, it indicates that the signal type of in/out of phase of the stereo signal in the audio frame is the near out of phase signal; or vice versa. [0170] A value range of the second threshold may be, for example, [0.8, 1.2], and the second threshold may be equal to, for example, 0.8, 0.85, 0.9, 1, 1.1, or 1.18.), obtaining a coded stream based on the two decorrelation processed channel signals, and writing the flag bit into the coded stream ([0099] For example, in a conventional MS encoding technology, left and right channel signals are first downmixed to obtain a mid-channel signal and a side channel signal. For example, L indicates the left channel signal, and R indicates the right channel signal. In this case, the mid channel signal is 0.5×(L+R), and the mid channel signal indicates information about a correlation between the left channel and the right channel; and the side channel signal is 0.5×(L−R), and the side channel signal indicates information about a difference between the left channel and the right channel. Then, the mid channel signal and the side channel signal are separately encoded by using a mono encoding method. The mid channel signal is usually encoded by using a relatively large quantity of bits, and the side channel signal is usually encoded by using a relatively small quantity of bits. [0117] Time-domain downmix processing may be performed on the left and right channel signals in the current frame to obtain the primary and secondary channel signals in the current frame, and the primary and secondary channel signals are further encoded to obtain a bitstream. Further, a channel combination scheme flag (the channel combination scheme flag of the current frame is used to indicate the channel combination scheme for the current frame) for the current frame may be written into the bitstream, so that a decoding apparatus determines the channel combination scheme for the current frame based on the channel combination scheme flag of the current frame that is included in the bitstream.).
Wang further teaches “A value range of the first threshold may be, for example, (0.5, 1.0)” ([0164]), and does not teach: wherein a value of the first threshold is in a range of (-1, 0).
However, It would have been obvious to one of ordinary skilled in the art before the effective filling date of the invention was made, for modification of Wang teaching which is an analogues prior art to use first threshold range (-1, 0) rather than (0.5, 1.0) because the modification would have constituted the mere arrangement of old elements with each performing the same function it had been known to perform, the combination yielding no more than obtaining two decorrelation process signal in response to the first coefficient being less than a first threshold, one would expect from such an arrangement, improve similar devices in the same way (See Intel Corp. v. PACT XPP Schweiz AG, 61 F.4th 1373, 1380-81, 2023 USPQ2d 297 (Fed. Cir. 2023)).
Regarding Claim 2, Wang teaches: The stereo audio signal processing method of claim 1, wherein the first decorrelation processing method comprises a first Mid/Side down-mixing processing (See rejection of claim 1 and [0099] For example, in a conventional MS encoding technology, left and right channel signals are first downmixed to obtain a mid-channel signal and a side channel signal. For example, L indicates the left channel signal, and R indicates the right channel signal. In this case, the mid channel signal is 0.5×(L+R), and the mid channel signal indicates information about a correlation between the left channel and the right channel; and the side channel signal is 0.5×(L−R), and the side channel signal indicates information about a difference between the left channel and the right channel. Then, the mid channel signal and the side channel signal are separately encoded by using a mono encoding method. The mid channel signal is usually encoded by using a relatively large quantity of bits, and the side channel signal is usually encoded by using a relatively small quantity of bits. [0117] Time-domain downmix processing may be performed on the left and right channel signals in the current frame to obtain the primary and secondary channel signals in the current frame, and the primary and secondary channel signals are further encoded to obtain a bitstream. Further, a channel combination scheme flag (the channel combination scheme flag of the current frame is used to indicate the channel combination scheme for the current frame) for the current frame may be written into the bitstream, so that a decoding apparatus determines the channel combination scheme for the current frame based on the channel combination scheme flag of the current frame that is included in the bitstream.).
Regarding Claim 3, Wang teaches: The stereo audio signal processing method of claim 2, wherein the first Mid/Side down-mixing processing comprises: processing the left channel signal and the right channel signal to obtain a primary channel signal and a secondary channel signal based on a formula Ⅰ, wherein, the formula Ⅰ is:
Mid (n) =
(
L
n
+
R
n
)
/
2
Sid (n) =
L
n
-
R
(
n
)
/
2
wherein the Mid(n) is the primary channel signal, the Sid(n) is the secondary channel signal, the L(n) is the left channel signal, and the R(n) is the right channel signal (See rejection of claim 1and [0099] For example, in a conventional MS encoding technology, left and right channel signals are first downmixed to obtain a mid-channel signal and a side channel signal. For example, L indicates the left channel signal, and R indicates the right channel signal. In this case, the mid channel signal is 0.5×(L+R), and the mid channel signal indicates information about a correlation between the left channel and the right channel; and the side channel signal is 0.5×(L−R), and the side channel signal indicates information about a difference between the left channel and the right channel. Then, the mid channel signal and the side channel signal are separately encoded by using a mono encoding method. The mid channel signal is usually encoded by using a relatively large quantity of bits, and the side channel signal is usually encoded by using a relatively small quantity of bits.).
Wang do not teach: The stereo audio signal processing method of claim 2, wherein the first Mid/Side down-mixing processing comprises: processing the left channel signal and the right channel signal to obtain a primary channel signal and a secondary channel signal based on a formula Ⅰ, wherein, the formula Ⅰ is:
Mid (n) =
(
L
n
-
R
n
)
/
2
Sid (n) =
L
n
+
R
(
n
)
wherein the Mid(n) is the primary channel signal, the Sid(n) is the secondary channel signal, the L(n) is the left channel signal, and the R(n) is the right channel signal.
However, It would have been obvious to one of ordinary skilled in the art before the effective filling date of the invention was made, for modification of Wang teaching to use Mid (n) =
(
L
n
-
R
n
)
/
2
, Sid (n) =
L
n
+
R
(
n
)
, instead Mid (n) =
(
L
n
+
R
n
)
/
2
Sid (n) =
L
n
-
R
(
n
)
/
2
because the modification would have constituted the mere arrangement of old elements with each performing the same function it had been known to perform, the combination yielding no more than processing the left channel signal and the right channel signal to obtain a primary channel signal and a secondary channel signal based on a formula, one would expect from such an arrangement, improve similar devices in the same way (See Intel Corp. v. PACT XPP Schweiz AG, 61 F.4th 1373, 1380-81, 2023 USPQ2d 297 (Fed. Cir. 2023)).
Regarding Claim 10, Wang teaches: A stereo audio signal processing method, performed by a decoding device, comprising: obtaining a coded stream transmitted by a coding device ([0589] 910. After obtaining the coding mode stereo_tdm_coder_type of the current frame, the encoding apparatus performs time-domain downmix processing on the left and right channel signals in the current frame based on a time-domain downmix processing method corresponding to the coding mode of the current frame, to obtain the primary channel signal and the secondary channel signal in the current frame. [0615] Certainly, the apparatus 1100 may further include a transceiver 1130 configured to receive and send data. [0619] Further, the apparatus 1100 may further include a transceiver 1130. The transceiver 1130 may be, for example, configured to receive and send related data (for example, an instruction, a channel signal, or a bitstream). [0621] For example, when the apparatus 1100 performs related steps of the foregoing encoding, the apparatus 1100 may be referred to as an encoding apparatus (or an audio encoding apparatus). When the apparatus 1100 performs related steps of the foregoing decoding, the apparatus 1100 may be referred to as a decoding apparatus (or an audio decoding apparatus).); determining two decorrelation processed channel signals (primary channel signal and the secondary channel signal ) and a flag bit (channel combination ratio factor based on the channel combination scheme flag) based on the coded stream ([0588] It is assumed that the correlated signal channel combination scheme is represented by 0 and the anticorrelated signal channel combination scheme is represented by 1. In this case, the joint flag of the channel combination scheme flags of the previous frame and the current frame has the following four cases: (01), (11), (10), and (00), and the coding mode of the current frame is determined as: a correlated signal coding mode, an anticorrelated signal coding mode, a correlated-to-anticorrelated signal coding switching mode, and an anticorrelated-to-correlated signal coding switching mode. [0592] In one embodiment, bit allocation may be first performed for encoding of the primary channel signal and encoding of the secondary channel signal based on parameter information obtained in encoding of a primary channel signal and/or a secondary channel signal in the previous frame and a total quantity of bits for encoding the primary channel signal and the secondary channel signal. Then, the primary channel signal and the secondary channel signal are separately encoded based on a result of the bit allocation, to obtain an encoded index of primary channel encoding and an encoded index of secondary channel encoding. Primary channel encoding and secondary channel encoding may be implemented by using any mono audio encoding technology, which is not further described herein. [0593] 912. The encoding apparatus selects a corresponding encoded index of a channel combination ratio factor based on the channel combination scheme flag and writes the encoded index into a bitstream, and writes the encoded primary channel signal, the encoded secondary channel signal, and the channel combination scheme flag of the current frame into the bitstream. [0595] In addition, the encoded primary channel signal, the encoded secondary channel signal, and the channel combination scheme flag of the current frame are written into the bitstream. It may be understood that there is no sequence for performing the bitstream writing operation.); and in response to the flag bit being a first value, obtaining a reconstructed audio signal by reconstructing the two decorrelation processed channel signals using a first decorrelation (based on a channel combination ratio factor of the anticorrelated signal channel combination scheme for the current frame, to obtain the reconstructed left and right channel signals in the current frame) reconstructing method, and outputting the reconstructed audio signal ([0245] performing time-domain upmix processing on the decoded primary and secondary channel signals in the current frame based on a channel combination ratio factor of the anticorrelated signal channel combination scheme for the current frame, to obtain the reconstructed left and right channel signals in the current frame; or performing time-domain upmix processing on the decoded primary and secondary channel signals in the current frame based on the channel combination ratio factor of the anticorrelated signal channel combination scheme for the current frame and a channel combination ratio factor of an anticorrelated signal channel combination scheme for the previous frame, to obtain the reconstructed left and right channel signals in the current frame. [0636] a decoding unit 1250 configured to: perform decoding based on the bitstream, to obtain decoded primary and secondary channel signals in the current frame; and perform time-domain upmix processing on the decoded primary and secondary channel signals in the current frame based on time-domain upmix processing corresponding to the decoding mode of the current frame, to obtain reconstructed left and right channel signals in the current frame.).
Regarding Claim 12, Wang teaches: The stereo audio signal processing method of claim 10, further comprising: in response to the flag bit being a second value (joint flag of the channel combination scheme flags of the previous frame and the current frame has the following four cases: (01), (11), (10), and (00)), obtaining a reconstructed audio signal by reconstructing the two decorrelation processed channel signals using a second decorrelation (based on the channel combination ratio factor of the anticorrelated signal channel combination scheme for the current frame and a channel combination ratio factor of an anticorrelated signal channel combination scheme for the previous frame, to obtain the reconstructed left and right channel signals in the current frame) reconstructing method, and outputting the reconstructed audio signal (See rejection of claim 10 and specifically [0588] It is assumed that the correlated signal channel combination scheme is represented by 0 and the anticorrelated signal channel combination scheme is represented by 1. In this case, the joint flag of the channel combination scheme flags of the previous frame and the current frame has the following four cases: (01), (11), (10), and (00), and the coding mode of the current frame is determined as: a correlated signal coding mode, an anticorrelated signal coding mode, a correlated-to-anticorrelated signal coding switching mode, and an anticorrelated-to-correlated signal coding switching mode.).
Regarding Claim 14, Wang teaches: The stereo audio signal processing method of claim 10, further comprising: in response to the flag bit being a third value(joint flag of the channel combination scheme flags of the previous frame and the current frame has the following four cases: (01), (11), (10), and (00)), determining the two decorrelation processed channel signals as a reconstructed audio signal (See rejection of claim 12).
Regarding Claim 17, Wang teaches: A communication apparatus, comprising a processor and a memory, storing a computer program executable by the processor: wherein the processor is configured to perform: determining a first cross-correlation coefficient for a left channel signal and a right channel signal of a current frame of a stereo audio signal; and in response to the first cross-correlation coefficient being less than a first threshold, obtaining two decorrelation processed channel signals by using a first decorrelation processing method to decorrelate the current frame of the stereo audio signal, calculating a second cross-correlation coefficient for the two decorrelation processed channel signals, and in response to the first cross-correlation coefficient being less than the second cross-correlation coefficient, determining a flag bit to be a first value, obtaining a coded stream based on the two decorrelation processed channel signals, and writing the flag bit into the coded stream, wherein a value of the first threshold is in a range of (-1, 0). (see rejection of claim 1 and [0617] In one embodiment, steps in the foregoing methods can be implemented by using a hardware integrated logical circuit in the processor 1110, or by using instructions in a form of software. The processor 1110 may be a general purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or another programmable logic device, a discrete gate or a transistor logic device, or a discrete hardware component. The processor 1110 may implement or perform the methods, the steps, and the logical block diagrams disclosed in the embodiments of the present invention. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. Steps of the methods disclosed with reference to the embodiments described herein may be directly executed and accomplished by using a hardware decoding processor, or may be executed and accomplished by using a combination of hardware and software modules in the decoding processor. [0618] The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory 1120. For example, the processor 1110 may read information in the memory 1120, and complete the steps in the foregoing methods in combination with hardware of the processor 1110.).
Regarding Claim 18, Wang teaches: A communication apparatus, comprising a processor and a memory, storing a computer program executable by the processor: wherein the processor is configured to perform the method of claim 10 (See rejection of claim 10 and [0617] In one embodiment, steps in the foregoing methods can be implemented by using a hardware integrated logical circuit in the processor 1110, or by using instructions in a form of software. The processor 1110 may be a general purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or another programmable logic device, a discrete gate or a transistor logic device, or a discrete hardware component. The processor 1110 may implement or perform the methods, the steps, and the logical block diagrams disclosed in the embodiments of the present invention. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. Steps of the methods disclosed with reference to the embodiments described herein may be directly executed and accomplished by using a hardware decoding processor, or may be executed and accomplished by using a combination of hardware and software modules in the decoding processor. [0618] The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory 1120. For example, the processor 1110 may read information in the memory 1120, and complete the steps in the foregoing methods in combination with hardware of the processor 1110.).
Regarding Claim 19, Wang teaches: A communication apparatus, comprising: a processor and an interface circuit; wherein the interface circuit, is configured to receive code instructions and transmit the code instructions to the processor; and the processor, is configured to execute the code instructions to perform the method of claim 1 (See rejection of claim 1 and [0617] In one embodiment, steps in the foregoing methods can be implemented by using a hardware integrated logical circuit in the processor 1110, or by using instructions in a form of software. The processor 1110 may be a general purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or another programmable logic device, a discrete gate or a transistor logic device, or a discrete hardware component. The processor 1110 may implement or perform the methods, the steps, and the logical block diagrams disclosed in the embodiments of the present invention. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. Steps of the methods disclosed with reference to the embodiments described herein may be directly executed and accomplished by using a hardware decoding processor, or may be executed and accomplished by using a combination of hardware and software modules in the decoding processor. [0618] The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory 1120. For example, the processor 1110 may read information in the memory 1120, and complete the steps in the foregoing methods in combination with hardware of the processor 1110.).
Regarding Claim 20, Wang teaches: A communication apparatus, comprising: a processor; and an interface circuit; wherein the interface circuit, is configured to receive code instructions and transmit the code instructions to the processor; and the processor, is configured to execute the code instructions to perform the method of claim 10. (See rejection of claim 10 and [0617] In one embodiment, steps in the foregoing methods can be implemented by using a hardware integrated logical circuit in the processor 1110, or by using instructions in a form of software. The processor 1110 may be a general purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or another programmable logic device, a discrete gate or a transistor logic device, or a discrete hardware component. The processor 1110 may implement or perform the methods, the steps, and the logical block diagrams disclosed in the embodiments of the present invention. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. Steps of the methods disclosed with reference to the embodiments described herein may be directly executed and accomplished by using a hardware decoding processor, or may be executed and accomplished by using a combination of hardware and software modules in the decoding processor. [0618] The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory 1120. For example, the processor 1110 may read information in the memory 1120, and complete the steps in the foregoing methods in combination with hardware of the processor 1110.).
Regarding Claim 21, Wang teaches: A non-transitory computer-readable storage medium storing instructions that when executed by a processor, cause the processor to perform the method of claim 1 (See rejection of claim 1 and [0617] In one embodiment, steps in the foregoing methods can be implemented by using a hardware integrated logical circuit in the processor 1110, or by using instructions in a form of software. The processor 1110 may be a general purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or another programmable logic device, a discrete gate or a transistor logic device, or a discrete hardware component. The processor 1110 may implement or perform the methods, the steps, and the logical block diagrams disclosed in the embodiments of the present invention. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. Steps of the methods disclosed with reference to the embodiments described herein may be directly executed and accomplished by using a hardware decoding processor, or may be executed and accomplished by using a combination of hardware and software modules in the decoding processor. [0618] The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory 1120. For example, the processor 1110 may read information in the memory 1120, and complete the steps in the foregoing methods in combination with hardware of the processor 1110.).
Regarding Claim 22, Wang teaches: A non-transitory computer-readable storage medium storing instructions that when executed by a processor, cause the processor to perform the method of claim 10 (See rejection of claim 10 and [0617] In one embodiment, steps in the foregoing methods can be implemented by using a hardware integrated logical circuit in the processor 1110, or by using instructions in a form of software. The processor 1110 may be a general purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or another programmable logic device, a discrete gate or a transistor logic device, or a discrete hardware component. The processor 1110 may implement or perform the methods, the steps, and the logical block diagrams disclosed in the embodiments of the present invention. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. Steps of the methods disclosed with reference to the embodiments described herein may be directly executed and accomplished by using a hardware decoding processor, or may be executed and accomplished by using a combination of hardware and software modules in the decoding processor. [0618] The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory 1120. For example, the processor 1110 may read information in the memory 1120, and complete the steps in the foregoing methods in combination with hardware of the processor 1110.).
Allowable Subject Matter
Claims 4-9, 11, and 13, objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art of records Melkote et al.(US 2015/0380000 A1) teach: Signal Decorrelation In An Audio Processing System.
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/MOHAMMAD K ISLAM/Primary Examiner, Art Unit 2653