DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1-2, 5-6, 10, 13-14, 16, 18-19, 22-23, 26, 28-29, 31-32, 36, 39 and 41 are currently pending in the present application. Claims 1, 18 and 31 are original; claims 2, 5-6, 10, 13-14, 16, 19, 22-23, 26, 28-29, 32, 36, 39 and 41 are currently amended; and claims 3-4, 7-9, 11-12, 15, 17, 20-21, 24-25, 27, 30, 33-35, 37-38, 40 and 42 are canceled. The amendment dated May 29, 2024 has been entered into the record.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1124 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 41 is objected to because of the following informalities:
In claim 41 lines 1-2, “the array substrate claim 1” should be “the array substrate of claim 1”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 31 and 36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20130215344, hereinafter “Kim”).
Regarding claim 1, Kim discloses an array substrate (Figs. 1-7; see Paras. [0032]-[0038] identifying the embodiment shown in Figs. 1-7), comprising:
a base substrate (110; Para. [0078]);
a plurality of gate lines (121; Para. [0078]) on a side of the base substrate, and extending along a first direction (the horizontal direction in Fig. 6);
a plurality of data lines (171a, 171b; Para. [0087]), wherein a main body direction of the plurality of data lines extends along a second direction (see the vertical direction in Fig. 6), and an orthographic projection of each of the plurality of data lines on the base substrate is curved in shape (see Fig. 6);
a plurality of pixel electrodes (191a, 191b; Para. [0063]), wherein an orthographic projection of the pixel electrodes on the base substrate is between orthographic projections of adjacent data lines on the base substrate (see Fig. 6); each pixel electrode comprises a plurality of slits (see slits formed between 191), and an extension direction of an orthographic projection of the slits on the base substrate is identical to an extension direction of the orthographic projection of adjacent data line on the base substrate (see Figs. 6-7).
Regarding claim 31, Kim discloses the limitations of claim 1 above, and further discloses wherein the orthographic projection of the gate line on the base substrate is on a side of the orthographic projection of the pixel electrode on the base substrate (see Figs. 6-7).
Regarding claim 36, Kim discloses the limitations of claim 31 above, and further discloses wherein each pixel electrode comprises: a first sub-electrode portion (the first upper portion of the pixel electrode in Fig. 6, with a slope of +1), a second sub-electrode portion (the second upper portion of the pixel electrode in Fig. 6, with a slope of -1), a third sub-electrode portion (the first lower portion of the pixel electrode in Fig. 6, with a slope of -1), and a fourth sub-electrode portion (the second lower portion of the pixel electrode in Fig. 6, with a slope of +1) sequentially distributed in the second direction;
an extension direction of the first sub-electrode portion is different from an extension direction of the second sub-electrode portion (Fig. 6); an extension direction of the third sub-electrode portion is different from an extension direction of the fourth sub-electrode portion (Fig. 6);
wherein the extension direction of the first sub-electrode is identical to the extension direction of the fourth sub-electrode portion (Fig. 6); the extension direction of the second sub-electrode portion is identical to the extension direction of the third sub-electrode portion (Fig. 6);
wherein each data line comprises:
a first data portion (171a for the first upper portion) located on a side of the first sub-electrode portion and extending in a direction same as the extension direction of the first sub-electrode portion;
a second data portion (171a for the second upper portion) located on a side of the second sub-electrode portion and extending in a direction same as the extension direction of the second sub-electrode portion;
a third data portion (171a for the first lower portion) located on a side of the third sub-electrode portion and extending in a direction same as the extension direction of the third sub-electrode portion; and
a fourth data portion (171a for the second upper portion) located on a side of the fourth sub-electrode portion and extending in a direction same as the extension direction of the fourth sub-electrode portion;
wherein the second data portion is directly connected with the third data portion (Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen et al. (US 20220334430, hereinafter “Chen”).
Regarding claim 39, Kim discloses the limitations of claim 31 above
each pixel electrode comprises: a fifth sub-electrode portion (the first upper portion of the pixel electrode in Fig. 6, with a slope of +1), a sixth sub-electrode portion (the second upper portion of the pixel electrode in Fig. 6, with a slope of -1), and a seventh sub-electrode portion (the first lower portion of the pixel electrode in Fig. 6, with a slope of -1) which are distributed in sequence in the second direction; an extension direction of the fifth sub-electrode portion is identical to an extension direction of the seventh sub-electrode portion (Fig. 6); an extension direction of the sixth sub-electrode portion is different from the extension direction of the fifth sub-electrode portion (Fig. 6);
wherein each data line comprises:
a ninth data portion (171a for the first upper portion) located on a side of the fifth sub-electrode portion and extending in a direction same as the extension direction of the fifth sub-electrode portion;
a tenth data portion (171a for the second upper portion) located on a side of the sixth sub-electrode portion and extending in a direction same as the extension direction of the sixth sub-electrode portion; and
an eleventh data portion (171a for the first lower portion) located on a side of the seventh sub-electrode portion and extending in a direction same as the extension direction of the seventh sub-electrode portion.
Kim does not explicitly disclose an extension length of the sixth sub-electrode portion is greater than an extension length of the fifth sub-electrode portion, and the extension length of the sixth sub-electrode portion is greater than an extension length of the seventh sub-electrode portion.
However, Chen teaches providing subpixels having different shapes and sizes (Fig. 9A; Para. [0129]), where an extension length of one sub-electrode portion is greater than an extension length of another sub-electrode portion (Fig. 9A).
It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to modify the pixel electrode as disclosed by Kim with the teachings of Chen, wherein an extension length of the sixth sub-electrode portion is greater than an extension length of the fifth sub-electrode portion, and the extension length of the sixth sub-electrode portion is greater than an extension length of the seventh sub-electrode portion, for the purpose of improving the display effect (Chen: Para. [0129]).
Claim 41 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kang et al. (US 20170123280, hereinafter “Kang”).
Regarding claim 41, Kim discloses the limitations of claim 1 above, and further discloses a display panel (Para. [0075] “a liquid crystal panel assembly”), comprising the array substrate, and further comprising an opposing substrate (200) arranged as opposed to the array substrate.
Kim does not explicitly disclose the opposing substrate comprises a common electrode layer.
However, Kang teaches a similar display panel (Figs. 1-2), wherein an opposing substrate comprises a common electrode layer (3000 includes 340; Para. [0098]).
It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to modify the display panel as disclosed by Kim with the teachings of Kang, wherein the opposing substrate comprises a common electrode layer, for the purpose of forming an electric filed (Kang: Para. [0103]) and as conventionally known in the art.
Allowable Subject Matter
Claims 2, 5-6, 10, 13-14, 16, 18-19, 22-23, 26, 28-29 and 32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Kim discloses the limitations of claim 1 above, and further discloses wherein an orthographic projection of the gate lines on the substrate passes through an central area of the orthographic projection of the pixel electrodes on the base substrate (see Fig. 6);
each pixel electrode comprises a first gap (the gap formed between the upper pixel electrode and the lower pixel electrode in Fig. 6) in an area where the gate lines are located; each pixel electrode comprises: a first pixel electrode (choose the pixel electrodes formed on the upper side of 121) located on one side of the gate line, a second pixel electrode (choose the pixel electrodes formed on the lower side of 121) on the other side of the gate line, and a connecting portion (see a branch pixel electrode formed in the gap and connecting the upper and lower pixel electrodes) connecting at least a part of the first pixel electrode with at least a part of the second pixel electrode;
wherein the array substrate further comprises: a plurality of transistors (Qa, Qb; Paras. [0061], [0094]); wherein the pixel electrodes are electrically connected with the data lines through the plurality of transistors (Fig. 6 and Para. [0061]);
the first pixel electrode comprises: a first sub-pixel electrode (191a1) distributed along the second direction, a second sub-pixel electrode (191b2) distributed along the second direction;
the second pixel electrode comprises: a third sub-pixel electrode (191b3) distributed along the second direction, a fourth sub-pixel electrode (191b6) distributed along the second direction;
wherein the second sub-pixel electrode is located on one side the first sub-pixel electrode far away from the data line (see the data line 171a in Fig. 6) that is electrically connected with the first sub-pixel electrode, and the fourth sub-pixel electrode is located on one side of the third sub-pixel electrode far away from the data line that is electrically connected with the third sub-pixel electrode (see Fig. 6); and
one of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected with one of the third sub-pixel electrode and the fourth sub-pixel electrodes through the connecting portion (see Fig. 6).
However, Kim fails to explicitly disclose, in light of the specification, “the first sub-pixel electrode and the fourth sub-pixel electrode are electrically connected through the connecting portion in a layer where the pixel electrodes are located; the second sub-pixel electrode is independent of the third sub-pixel electrode in the layer where the pixel electrodes are located”. The examiner considered Wang et al. (US 20240353722, hereinafter “Wang”) and Tominaga (US 20230185142). For example, Wang teaches an array substrate having subpixel electrodes disposed between a plurality of data lines (Fig. 2; Para. [0083]), but fails to explicitly disclose the first sub-pixel electrode and the fourth sub-pixel electrode are electrically connected through the connecting portion; the second sub-pixel electrode is independent of the third sub-pixel electrode. The prior art of Kim, Kang, Wang, Chen and Tominaga, applied alone or in combination fails to teach or suggest the combination and arrangement of elements recited in Applicant's claim 2.
Dependent claims 5-6, 10, 13-14, 16, 18-19, 22-23, 26 and 28-29 are allowable by virtue of their dependence on claim 2.
Regarding claim 32, Kim discloses the limitations of claim 31 above, and further discloses a first conductive layer (138; Para. [0186]) arranged on a side facing the base substrate, of the pixel electrode, and a fifth common wire (131b; Para. [0186]) in a layer same as the layer where the gate liens are located (Para. [0186] teaching 121 and 131b located in a same layer on 100); the first conductive layer is electrically connected with the fifth common wire through a conduction hole (141 in Fig. 15).
And Ding et al. (US 20200241369, hereinafter “Ding”) further discloses a common wire comprises a first common convex portion on a side facing the gate lines (52 includes convex portions on a side facing 51 in Figs. 2 and 9c; Para. [0051] “as shown in FIG. 2a, the first storage electrode 11 further overlaps the common electrode line 52 to form a second storage capacitance”).
However, Kim and Ding fail to explicitly disclose, in light of the specifications, “wherein the fifth common wire comprises a first common convex portion on a side facing the gate lines, of the fifth common wire; at least parts of orthographic projection of the first common convex portion on the base substrate overlaps at least parts of orthographic projection of the conduction hole on the base substrate; wherein each gate line comprises a first notch on a side facing the fifth common wire, of the gate line, the first notch is opposite to the first common convex portion; wherein one side of the pixel electrode is provided with a fifth lap portion; each gate line comprises a second notch on a side facing the fifth common wire, of the gate line; an orthographic projection of the second notch on the base substrate covers the orthographic projection of the fifth lap portion on the base substrate”. The examiner further considered the prior art of Kim, Ding, Kang, Wang, Chen and Tominaga. However, the prior art applied alone or in combination fails to teach or suggest the combination and arrangement of elements recited in Applicant's claim 32.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN Y JUNG whose telephone number is (469)295-9076. The examiner can normally be reached on Monday - Friday, 9:00 am - 5:00 pm.
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/JONATHAN Y JUNG/Primary Examiner, Art Unit 2871
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