DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 8/31/2026 is acknowledged.
Claims 12-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/31/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
First side and second side appear twice within the claim making the antecedent basis of second side surface unclear.
Recitation of:
a lower gate portion and a side gate portion arranged along the second side surface of the top channel nanosheet, wherein the side gate portion of the bottom gate electrode defines a via contact portion protruding outside the top gate electrode and the first side surface of the top channel nanosheet.
It is unclear if the bottom gate defines the first side surface of the top nanoseheet or the protruding is outside of the first side surface.
It appear it should be:
a lower gate portion and a side gate portion arranged along the second side surface of the top channel nanosheet, wherein the side gate portion of the bottom gate electrode defines a via contact portion protruding outside both of the top gate electrode and the first side surface of the top channel nanosheet.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-11 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Hekmatshoartabari 20210349691.
a. As to claim 1,Hekmatshoartabari teaches A complementary field-effect transistor, CFET, device (figure 23 paragraph 110 and 46-51) comprising: a bottom FET device (device corresponding to 131) and a top FET device (device corresponding to 137) stacked on top of the bottom FET device (see e.g. figure 23b),the bottom FET device (items corresponding to item 131) comprising a bottom channel nanostructure (131 abstract) having a first side surface (top, bottoms or one of the sides) oriented in a first direction and a second side surface (the side opposite) oriented in a second direction opposite the first direction (by definition), and a bottom gate electrode (350) configured to define a tri-gate or a gate-all-around with respect to the bottom channel nanostructure ( wrap around gate a wraparound gate comprises a trigate as well), the bottom gate electrode (350) comprising a side gate portion (360 along the top or side) arranged along the first side surface (by definition) of the bottom channel nanostructure, and the top FET device (device relative to items 137) comprising a top channel nanosheet (item 137 abstract) having a first side surface (side commensurate with the first side of the bottom device) oriented in the first direction and a second side surface (side opposite the first) oriented in the second direction, and a top gate electrode (360) configured to define a tri-gate with respect to the top channel nanosheet (item 360 can be consider a trigate and wrap around gate a wraparound gate comprises a tri gate) and comprising an upper gate portion (part at the top surface near 380 and adjacent 2220), a lower gate portion (portion of 360/350 near 230) and a side gate portion (portion adjacent to the side) arranged along the second side surface (by definition) of the top channel nanosheet wherein the side gate portion (350 figure 23b) of the bottom gate electrode (350 ) defines a via contact portion protruding outside both the top gate electrode (350 on the left defines a via contact for 2210 is out 360 below 230) and the first side surface (item 350 is outside 185 side which can be the first side surface) of the top channel nanosheet ( it is also out the channels 137); and a top gate contact via (2220) for coupling the top gate electrode (360) to a first conductive line (see figure 23a item 2220 across the top) over the top FET device (figure 23a 23b relative positions) and a bottom gate contact via (parts of 350 that extend through 260/230 and2210) for coupling the via contact portion (a portion of 350) of the bottom gate electrode (350) to a second conductive line (top of 2210 shown in figure 23a and 23f) over the top FET device (see figure 23).
b. AS to claim 2, Hekmatshoartabari teaches further comprising a dielectric layer (items 260 and 230 or 235 figure 23f and 23b) arranged between the bottom gate electrode (item 235 and 230 between 350 and 360) and the top gate electrode, wherein the bottom gate contact via (item 350 extends through at least 235 and by definition item 350 extends through 230/260) extends through the dielectric layer.
c. As to claim 3, Hekmatshoartabari teaches wherein the top channel nanosheet (137) is arranged directly above the bottom channel nanostructure (131).
d. As to claim 4, Hekmatshoartabari wherein the first side surface (131 first side) of the bottom channel nanostructure (131) is aligned with the first side surface (first side of item 137) of the top channel nanosheet (137).
e. As to claim 5, Hekmatshoartabari teaches the channels are nanosheets (abstract).
f. As to claim 6, Hekmatshoartabari teaches wherein the bottom channel nanosheet (131) and the top channel nanosheet (137) have the same width (figure 23 they are the same width and both nanosheets abstract and figure 23).
g. As to claim 7, Hekmatshoartabari teaches wherein the first side surface (first side of item 137) of the bottom channel nanosheet (first side of item 131) is aligned with the first side surface (first side of item 137) of the top channel nanosheet (137), and the second side surface (second side of item 131) of the bottom channel nanosheet (131) is aligned with the second side surface (second side of 137) of the top channel nanosheet (137).
h. As to claim 9, there is no distinction defined between a fin and a nanosheet Hekmatshoartabari therefore teaches wherein the bottom channel nanostructure is a first fin structure (item 131 can be considered a fin since there is no fixed definition), and wherein the bottom gate electrode (369) extends across the first fin structure (item 350 extends across the top) to define a tri-gate with respect to the first fin structure ( figure 23).
i. As to claim 10 alongside does not imply a edge or a side surface the top surface and bottom surfaces are sides thus Hekmatshoartabari teaches wherein the bottom FET device (items 131) further comprises a second fin structure (131) arranged alongside the first fin structure (there is a second nanosheet which can be considered a fin above or a long a top side of the first fin), and wherein the bottom gate electrode (350) extends across the first fin and second fin structures (131) to define a tri-gate with respect to each of the first and second fin structures (figure 23).
j. As to claim 11, Hekmatshoartabari teaches wherein the top channel nanosheet (137) is arranged directly above the first and the second fin structure (items 131).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng A Routability-Driven Complimentary-FET(CFET) Standard Cell Synthesis Framework using SM.
AS to claims 1 and 5, Cheng teaches A complementary field-effect transistor, CFET, device (figure 1) comprising: a bottom FET device (NMOS) and a top FET device (PMOS) stacked on top of the bottom FET device (figure 1),the bottom FET device (NMOS) comprising a bottom channel (bottom channel) having a first side surface (figure 1 left or right side) oriented in a first direction and a second side surface (opposite side) oriented in a second direction opposite the first direction, and a bottom gate electrode (lower PC) configured to define a tri-gate or a gate-all-around with respect to the bottom channel (NMOS channel), the bottom gate electrode (Lower PC) comprising a side gate portion (portion on the first side surface) arranged along the first side surface (by definition) of the bottom channel nanostructure, and the top FET device (PMOS) comprising a top channel (channel of pmos) having a first side surface (corresponding first side to the bottom) oriented in the first direction and a second side surface (side opposite) oriented in the second direction, and a top gate electrode (upper PC) configured to define a tri-gate with respect to the top channel (a wrap-around gate comprises a tri gate) and comprising an upper gate portion (top portion of gate), a lower gate portion (bottom portion of gate) and a side gate portion (side portion of gate along the second side) arranged along the second side surface (by definition) of the top channel nanosheet, wherein the side gate portion (edge portion of Lower pc) of the bottom gate electrode (lower pc) defines a via contact portion protruding outside the top gate electrode (region contact by CA outside upper PC ) and the first side surface (the first side can be define as the side on which the via is on) of the top channel nanosheet (figure 1); and a top gate contact via (CA contacting upper PC) for coupling the top gate electrode (CA contact MO routing track) to a first conductive line (124) over the top FET device (140) and a bottom gate contact via (CA contacting the Lower PC) for coupling the via contact portion (CA on lower pc) of the bottom gate electrode (Lower pc) to a second conductive line (MO routing) over the top FET device (see figure 1).
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Cheng does not explicitly state the channels are nanosheets, however nanosheets were known for such devices reference 21 SM Yasser Sherazi et al. 2019. Standard-cell design architecture options below 5mnnode: The ultimate scaling of FinFET and Nanosheet. InSPIE. International Society for Optics and Photonics.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the channels as nanosheet to use conventional channel structure to provide expected outcomes of confined carrier flow in the channel.
As to claim 8, Cheng teaches all around gates for the nmos since the gate is on every side.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rubin 20200126987 places vertical fins below nanosheet devices figure 1 and figure 3 paragraph 37).
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
