Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 19-38 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19, 29 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1).
As per claim 19, Wang teaches A method comprising:
determining, by one or more processors of a computing device, one or more characteristics of a gaming application executing at the one or more processors; (Wang [0061] The method 700 includes at block 705 determining a game state based on at least one game state indicator. The UE, or more precisely, a UE game application may determine the game state based on at least one game state indicator).
determining, by the one or more processors and based at least in part on the one or more characteristics, that the gaming application is in a loading state; (Wang [0049] FIG. 4 is a schematic diagram of an alternative example 400 of game state indicator based on a game API, according to aspects of the present disclosure. In one example aspect, FIG. 4 shows a game API 401, configured to indicate to an associated UE application module various states of a game application. An example of the associated UE application module is the Game-State Based NI Management Module The various game states may include a game loading state 4-1, a player authentication state 402, a game update state 403, a game loading state 405, a game player selection state 406, a game starting state 407, and the game complete state 408.)
Wang does not teach in response to determining that the gaming application is in the loading state, adjusting, by the one or more processors, at least one of: a clock speed of the one or more processors or a prioritization of the gaming application.
However, Kim teaches in response to determining that the gaming application is in the loading state, adjusting, by the one or more processors, at least one of: a clock speed of the one or more processors or a prioritization of the gaming application (Kim [0016] According to various embodiments, it is possible to increase the launching speed when the application is executed by increasing the priority for the process which is the launching target upon running the application to allow the process to be processed earlier than the other processes [0065] However, according to various embodiments, it is possible to increase the launching speed when the application is executed by increasing the priority for the process which is the launching target upon running the application to allow the process to be processed earlier than the other processes. Quick launching may be rendered possible by scheduling higher-priority processes using a high-performance CPU. [0115] According to an embodiment, largely two methods may be considered to shorten the launching time of application upon running the application: a dependency-based scheme of restrict other processes unnecessarily operating than the launching application and a priority-based scheme of maximizing the system operation clock for the launching target process. [0120] According to an embodiment, as another scheme for increasing the application launching speed, the priority-based scheme may raise the priority of the process, as the launching target, among the plurality of processes associated with the application when the application is launching, and at least one thread in the launching target process and, at the time of completion of the application launching, change the raised priority of the process and thread in the process back into the original priority. [0128] Since a quick response is needed for the process corresponding to the high-priority group and at least one thread in the process, a CPU (e.g., a high-performance CPU) with a first operation speed may be used to accelerate processing and hence application launching. In contrast, the process corresponding to the low-priority group and at least one thread in the process may be processed with a CPU (e.g., a low-performance CPU) with a second operation speed.)
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Kim with the system of Wang to prioritize a gaming application. One having ordinary skill in the art would have been motivated to use Kim into the system of Wang for the purpose of reducing the application launching time. (Kim paragraph 06)
As to claims 29 and 36, they are rejected based on the same reason as claim 19.
Claims 20, 30 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1) in further view of Chen (US 2017/0269667 A1).
As per claim 20, Wang and Kim do not teach wherein the one or more characteristics comprise patterns of usage of the one or more processors by the gaming application during execution at the one or more processors, and wherein determining that the gaming application is in the loading state further comprises:
determining, by the one or more processors and based at least in part on the patterns of usage of the one or more processors by the gaming application, that the gaming application is in the loading state.
However, Chen teaches wherein the one or more characteristics comprise patterns of usage of the one or more processors by the gaming application during execution at the one or more processors, and wherein determining that the gaming application is in the loading state further comprises:
determining, by the one or more processors and based at least in part on the patterns of usage of the one or more processors by the gaming application, that the gaming application is in the loading state. (Chen [0052] for classifying application program 10 phases, the observation derived from profiling the graphics processing unit command 12 is provided, and accordingly discrimination between GPU-sensitive phase, e.g. the rendering phase, and GPU-insensitive phase, e.g. the loading phase is made)
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Chen with the system of Wang and Kim to use pattern of usage of processors. One having ordinary skill in the art would have been motivated to use Chen into the system of Wang and Kim for the purpose of reducing energy consumption of graphics-intensive applications.(Chen paragraph 02)
As per claim 37, Wang and Kim do not teach wherein the one or more characteristics comprise one or more of: patterns of usage of the one or more processors by the gaming application during execution at the one or more processors, a pattern of functions invoked by the gaming application during execution at the one or more processors, a pattern of inputs received at an input device during execution of the gaming application at the one or more processors, or image data outputted for display at a display device by the gaming application, and wherein to determine that the gaming application is in the loading state, the instructions further cause the one or more processors to: determine, and based at least in part on one or more of: the patterns of usage of the one or more processors by the gaming application, pattern of functions invoked by the gaming application during execution at the one or more processors, the pattern of inputs received at an input device during execution of the gaming application at the one or more processors, or the image data outputted for display at a display device by the gaming application, that the gaming application is in the loading state.
However, Chen teaches patterns of usage of the one or more processors by the gaming application during execution at the one or more processors, (Chen [0052] for classifying application program 10 phases, the observation derived from profiling the graphics processing unit command 12 is provided, and accordingly discrimination between GPU-sensitive phase, e.g. the rendering phase, and GPU-insensitive phase, e.g. the loading phase is made)
a pattern of functions invoked by the gaming application during execution at the one or more processors,
a pattern of inputs received at an input device during execution of the gaming application at the one or more processors,
or image data outputted for display at a display device by the gaming application, and wherein to determine that the gaming application is in the loading state, the instructions further cause the one or more processors to:
determine, and based at least in part on one or more of:
the patterns of usage of the one or more processors by the gaming application,
pattern of functions invoked by the gaming application during execution at the one or more processors,
the pattern of inputs received at an input device during execution of the gaming application at the one or more processors, or
the image data outputted for display at a display device by the gaming application, that the gaming application is in the loading state.
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Chen with the system of Wang and Kim to use pattern of usage of processors. One having ordinary skill in the art would have been motivated to use Chen into the system of Wang and Kim for the purpose of reducing energy consumption of graphics-intensive applications.(Chen paragraph 02)
As to claim 30, it is rejected based on the same reason as claim 37.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1) in further view of Sharma (US 2019/0363954 A1).
As per claim 21, Wang and Kim do not teach determining, by the one or more processors and based at least in part on a pattern of functions invoked by the gaming application, that the gaming application is in the loading state.
However, Sharma teaches determining, by the one or more processors and based at least in part on a pattern of functions invoked by the gaming application, that the gaming application is in the loading state. (Sharma [claim 18] an application orchestrator and from an application provider, a request for loading an application comprising of a function sequence, wherein the function sequence comprises multiple functions to complete the application, wherein each function in the function sequence is executed in one of multiple instances of a particular function; identifying an instance chain of the functions to complete the application, wherein the instance chain comprises an instance for each function in the function sequence)
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Sharma with the system of Wang and Kim to use pattern of functions invoked by an application. One having ordinary skill in the art would have been motivated to use Sharma into the system of Wang and Kim for the purpose of deploying and running applications more efficiently in the cloud (Sharma paragraphs 13 and 16).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1) in further view of Goolkasian (US 2026/0127688 A1).
As per claim 22, Wang and Kim do not teach wherein the one or more characteristics comprise a pattern of inputs received at an input device during execution of the gaming application at the one or more processors, and wherein determining that the gaming application is in the loading state further comprises: determining, by the one or more processors and based at least in part on the pattern of inputs received at an input device, that the gaming application is in the loading state.
However, Goolkasian teaches wherein the one or more characteristics comprise a pattern of inputs received at an input device during execution of the gaming application at the one or more processors, and wherein determining that the gaming application is in the loading state further comprises: determining, by the one or more processors and based at least in part on the pattern of inputs received at an input device, that the gaming application is in the loading state. (Goolkasian [0165] In some examples, the application management component 114 can cause the interactable elements to be presented via a computing device (e.g., a merchant computing device, a kiosk, etc.) based at least in part on the sequence. In at least one example, the application management component 114 can maintain a sequence of such instant applications and triggering actions (such as worker actions and/or interactions) can initialize instant applications based at least in part on the sequence).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Goolkasian with the system of Wang and Kim to use pattern of inputs received at an input device. One having ordinary skill in the art would have been motivated to use Goolkasian into the system of Wang and Kim for the purpose of automatically downloading applications (Goolkasian paragraph 14).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1) in further view of Parekh (US 2020/0389516 A1).
As per claim 23, Wang and Kim do not teach wherein the one or more characteristics comprise image data outputted for display at a display device by the gaming application, and wherein determining that the gaming application is in the loading state further comprises: determining, by the one or more processors and based at least in part on the image data outputted for display at the display device, that the gaming application is in the loading state.
However, Parekh teaches wherein the one or more characteristics comprise image data outputted for display at a display device by the gaming application, and wherein determining that the gaming application is in the loading state further comprises: determining, by the one or more processors and based at least in part on the image data outputted for display at the display device, that the gaming application is in the loading state. (Parekh [claim 1] generate a plurality of custom machine images, wherein at least one of the plurality of customer machine images is configured with a first initialized application state for an application, and at least another one of the plurality of customer machine images is configured with a second initialized application state for the application, and the first initialized application state and second application states are different states of configuration for the application, wherein each of the custom machine images is generated based on at least a portion of the plurality of resources provisioned and booted with initialization code)
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Parekh with the system of Wang and Kim to use image data outputted for display. One having ordinary skill in the art would have been motivated to use Parekh into the system of Wang and Kim for the purpose of handling rogue spikes in application demand. (Parekh paragraph 03)
Claims 24 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1) in further view of Hawver (US 2014/0329589 A1).
As per claim 24, Wang and Kim do not teach determining, by the one or more processors, that the gaming application is performing one or more actions to prepare to provide an interactive gameplay environment for active gameplay.
However, Hawver teaches determining, by the one or more processors, that the gaming application is performing one or more actions to prepare to provide an interactive gameplay environment for active gameplay. (Hawver 0017] One embodiment of the subject disclosure can entail a processor that performs operations including detecting first speech of a first gamer of video games, determining a first identity of the first gamer according to a biometric feature of the first gamer, accessing a gaming account of the first gamer according to the first identity, determining from the gaming account a plurality of other gamers that have engaged in a gaming session with the first gamer, facilitating communications with gaming equipment to determine whether at least one gamer of the plurality of other gamers is available to engage in a new gaming session with the first gamer, determining from the gaming equipment that a second gamer of the plurality other gainers is available to engage in the new gaming session, presenting at a user interface a second identity of the second gamer, detecting second speech from the first gamer, determining from the second speech that the first gamer has requested to engage in the new gaming session with the second gamer, and configuring first equipment used by the first gamer according to a gaming profile retrieved from the gaming account in preparation for engaging in the new gaming session).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Hawver with the system of Wang and Kim to prepare to provide an interactive gameplay environment for active gameplay. One having ordinary skill in the art would have been motivated to use Hawver into the system of Wang and Kim for the purpose of configuring a gaming environment. (Hawver paragraph 01)
As to claim 31, it is rejected based on the same reason as claim 24.
Claims 25, 32 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1) in further view of Hariharakrishnan (US 2016/0098334 A1).
As per claim 25, Wang and Kim do not teach adjusting, by the one or more processors, a respective clock speed of at least one of: a central processing unit (CPU) or a graphics processing unit (GPU) of the one or more processors.
However, Hariharakrishnan teaches adjusting, by the one or more processors, a respective clock speed of at least one of: a central processing unit (CPU) or a graphics processing unit (GPU) of the one or more processors. (Hariharakrishnan [0240] In another example, the operating point of the mobile device 100 or 200 may be adjusted for more performance when the user executes a gaming application (e.g. a graphics intensive game) that may require a high performance on the mobile device 100 or 200. When the user plays the gaming application on the mobile device, the diagnostic application 116 or 216 is further configured to determine, based on performance-related data being collected during execution of the gaming application, whether the performance of the game on the mobile device 100 or 200 is acceptable or meets certain performance criteria in relation to the user playing the game. If it is detected that the mobile device 100 or 200 is not able to achieve a frame rate of more than 30 frames-per-second, then this information is fedback to the underlying hardware, e.g. the GPU driver, and corrective action may be taken to adjust the clock speed of the GPU higher. This will increase the performance of the game and provide a better user experience whilst the user plays the game).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Hariharakrishnan with the system of Wang and Kim to adjust clock speed of a processor. One having ordinary skill in the art would have been motivated to use Hariharakrishnan into the system of Wang and Kim for the purpose of adjusting a clock speed of a core of a multicore processor of user equipment and delivery apparatus in a fifth-generation network. (Trim paragraph 01)
As to claims 32 and 38, they are rejected based on the same reason as claim 25.
Claims 27 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1) in further view of Trim (US 2022/0066499 A1).
As per claim 27, Wang and Kim do not teach adjusting, by the one or more processors, the respective clock speed of at least one of: the CPU or the GPU of the one or more processors based at least in part on functions invoked by the gaming application in the loading state.
However, Trim teaches adjusting, by the one or more processors, the respective clock speed of at least one of: the CPU or the GPU of the one or more processors based at least in part on functions invoked by the gaming application in the loading state. (Trim [0070] FIG. 5 is a flowchart depicting operational steps of CPU clock management program 200, a program for dynamically adjusting a clock speed of a core of a multicore processor of user equipment, in accordance with embodiments of the present invention based on time, situation and nature of the environmental constrains. In one embodiment, CPU clock management program 200 initiates in response to user device 120 registering with CPU clock management via network 110. For example, CPU clock management program 200 initiates in response to a mobile device (e.g., user device 120) transmitting an authentication request to CPU clock management in a component of a 5G telecom network (e.g., network 110). In another embodiment, CPU clock management program 200 initiates in response to application 124 of user device 120. For example, CPU clock management program 200 is a client-side background application (e.g., application 124) that initiates in response a boot request [function request] of a mobile device (e.g., user device 120) that has powered on).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Trim with the system of Wang and Kim to adjust clock speed based on functions. One having ordinary skill in the art would have been motivated to use Trim into the system of Wang and Kim for the purpose of optimising the performance of a mobile device. (Trim paragraph 01)
As to claim 34, it is rejected based on the same reason as claim 27.
Claims 28 and 35 rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0093953 A1) in view of Kim (US 2020/0341805 A1) in further view of Fu (US 2006/0242433 A1).
As per claim 28, Wang and Kim do not teach a loading state CPU clock speed associated with the gaming application or a loading state GPU clock speed associated with the gaming application; and adjusting, by the one or more processors, the respective clock speed of at least one of: the CPU or the GPU of the one or more processors based at least in part on at least one of: the loading state CPU clock speed or the loading state GPU clock speed.
However, Fu teaches a loading state CPU clock speed associated with the gaming application or a loading state GPU clock speed associated with the gaming application; and adjusting, by the one or more processors, the respective clock speed of at least one of: the CPU or the GPU of the one or more processors based at least in part on at least one of: the loading state CPU clock speed or the loading state GPU clock speed. (Fu [0028] Please refer to FIG. 3. FIG. 3 illustrates a time-relation diagram of the invention flow during three phases. The first phase performs an estimation of the system loading. The first phase will estimate whether the system loading will become greater. The estimation time period is extremely short which may consist of approximately one to three seconds. When the first system loading is greater than the first threshold, then the estimated system loading becomes greater. Note that the first threshold can assign its own setting according to the demand of a design, for example, the first threshold can be set to 50%. As the estimated system loading is going to become greater, therefore the CPU clock speed must be adjusted to cope with a full speed of the system loading. When the current CPU clock speed is already lowered, the CPU clock speed must adjust back to the full speed, then step 110 will be executed afterwards; in step 110, when the current CPU clock speed has not been lowered or the CPU clock speed has already been adjusted back to the full speed, then the CPU clock speed can be maintained in the second time period, which means that after the second time period, the estimation of the system loading of the first phase can be carried out again to estimate whether the system loading has any great movement. The second time period in comparison is longer than the first time period. The second time period may require approximately 25 seconds to 35 seconds. If the first system loading in the first phase is not greater than the first threshold, then the system loading is estimated to maintain and not change, therefore the system loading can enter into the second phase [0029] The second phase is utilized for monitoring the system loading. The second phase can determine whether the system is in an overloading state or a stable condition. This is necessary to avoid the load of the system being small or idling at the stable condition in the first phase, but soon after the schedule will be executed and the system will enter into a state of a greater load, hence causing a misjudgment in the system loading state. Estimation time of the third time period in the second phase is longer and requires approximately 20 to 30 seconds. When the second system loading is greater than the second threshold, even though utilization rate of the CPU is not fully utilized, it can be determined that the system is at the overloading state. The second threshold can set its own setting according to the demand of the design, for example, the second threshold can be set to the first threshold*(1+(the full speed of the CPU-a current CPU clock speed)/(the full speed of the CPU-the lowest clock speed of the CPU)). In other words, the first threshold increases the percentage of a gap between the full speed and the lowest clock speed of the CPU occupied by a gap between the full speed and the current CPU clock speed, to become the second threshold. As the system is determined to be at the overloading state, therefore it is not suitable to reduce the CPU clock speed, thus the CPU clock speed must be adjusted to cope with the full speed of the system loading. Under the same principle, when the CPU present clock speed is already lowered, then the CPU clock speed needs to be adjusted back to the full speed, then step 110 will be executed afterwards; in step 110, if when the current CPU clock speed has not been lowered or the CPU clock speed has already been adjusted back to the full speed, then the CPU clock speed can be maintained in the second time period, which means that after the second time period, the estimation of the system loading of the first phase can be carried out again to estimate whether the system loading has any great movement, however this waiting time period can also be another fourth time period. The fourth time period can be greater than the third time period, yet the fourth time period is not equal to the second time period. Like the previous time periods, again the fourth time period can set its own setting according to the demand of the design. If the second system loading is not greater than the second threshold in the second phase, then the system loading is estimated to maintain and not change, therefore the system loading can enter the third phase. [0030] The third phase can estimate whether the system loading changes, similar to the first phase, estimate time of the fifth time period in the third phase is extremely short, it requires approximately 1 to 3 seconds. When the third system loading is greater than the third threshold, then the estimated system loading becomes greater. The third threshold can set its own setting according to the demand of the design, for example, the third threshold can be set to the same value as the first threshold, such as 50%, as the estimated system loading is going to become greater, therefore the CPU clock speed needs to be adjusted to cope with the full speed of the system loading, when the current CPU clock speed is already lowered, the CPU clock speed needs to adjust back the full speed, then step 110 will be executed afterwards; in step 110, when the current CPU clock speed has not been lowered or the CPU clock speed has already been adjusted back to the full speed, then the CPU clock speed can be maintained in the second time period, which means that after the second time period, the estimation of the system loading of the first phase can be carried out again to estimate whether the system loading has any great movement, however this waiting time period can also be another sixth time period. The sixth time period can be greater than the third time period, yet the sixth time period is not equal to the second time period, and again the sixth time period can set its own setting according to the demand of the design. If the third system loading is not greater than the third threshold in the third phase, then the system loading is estimated to maintain and not change, therefore the clock speed of the CPU can be lowered. At this time the CPU clock speed is determined whether it is greater than the lowest clock speed, if the CPU clock speed is equal to the lowest clock speed, then the CPU clock speed will be maintained at the lowest clock speed to reduce power consumption of the CPU. Many intervals of CPU clock speed can be utilized by realizing the following equation: ((the full speed of the CPU-the lowest clock speed of the CPU)/speed adjustment gap of the CPU). In other words, the CPU clock speed can be divided into m number of levels from the full speed to the lowest clock speed, and after the above-mentioned process, when each system loading conforming to three phases is smaller than an individual threshold, then the CPU clock speed can be lowered to a lower level. When the above-mentioned process is repeated, each system loading conforming to the three phases is smaller than an individual threshold, and then the CPU clock speed is lowered again to another lower level.[0031] After the above flow has executed, the flow returns to step 100 again. In estimating and determining the system loading state, the CPU clock speed adjusts accordingly to achieve a stable system operation and balanced power consumption.).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Fu with the system of Wang and Kim to adjust clock speed. One having ordinary skill in the art would have been motivated to use Fu into the system of Wang and Kim for the purpose of loading of the electronic appliance to achieve an effective power management. (Fu paragraph 02)
As to claim 35, it is rejected based on the same reason as claim 28.
Allowable Subject Matter
Claim 26 and 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230173382 A1 – disclose concurrently executing different instances of a game program, each instance employing a different set of hardware resources, including different local memory, such as the hardware resources of different servers or different GPUs. Based on a game state, the game streaming system streams rendered frames from a first set of hardware resources associated with the game level to a client device wherein the rendered frames, depicting a portion of a virtual environment. In response to an indication from the game program of a game level change to a new game level, the game streaming system transfers a player state to another set of hardware resources, and begins streaming rendered frames to the client device from the other of hardware resources.
US 7051219 B2 – discloses a method of scheduling a CPU in which a clock of the CPU is controlled depending upon the states of processes to reduce power consumption. The clock is controlled by substituting clock functions of an embedded system into a scheduler function, comparting a wait time until a scheduling is completed with the sum of an execution time given for satisfying a real-time condition and an error range of a permissible error of a scheduling, changing a clock state of a process depending on the compared result, calculating an elapsed time with respect to a difference between the changed scheduling clock and a scheduling clock before the change of clock to control the wait time Wk and setting the clock of the CPU using the value of a newly determined clock.
US 20140215497 A1 – discloses adjusting operation load of a mobile terminal is disclosed in the present invention, and the method comprises a step of acquiring a processor clock speed frequency, a battery remaining capacity or a processor temperature; a step of determining whether the processor clock speed frequency is higher than a first predetermined threshold value, whether the battery remaining capacity is lower than a second predetermined threshold value, or whether the processor temperature is higher than a third predetermined threshold value; a step of closing the application program is executed through a driver layer of the mobile terminal in accordance with the strategy to release resource and reduce the processor clock speed frequency if any one or all of the conditions above are yes.
US 20090319812 A1 – discloses a computing device based on execution load and a power saving preference. The power saving preference relates to responsiveness of the processors versus power consumption of the processors to manage battery life of the device. The processors and processor hardware components may be powered on and off based on a determined execution load for the processors and based on the power saving preference. For example, arithmetic logic units, caches, vectorization units, and units for graphics or multimedia support may be individually enabled or disabled based on the execution load and the power saving preference.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEHRAN KAMRAN whose telephone number is (571)272-3401. The examiner can normally be reached on 9-5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MEHRAN KAMRAN/ Primary Examiner, Art Unit 2196
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