DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakazawa et al. (US PG-Pub No.: 2021/0084249 A1, hereinafter, “Nakazawa”, also known as WO2019130702).
Regarding claim 1, Nakazawa discloses a light detection device (see Nakazawa, FIG. 19) comprising:
a first substrate portion (50+40+45+41, FIG. 19) having a pixel (41, ¶ [0127]) configured to photoelectrically convert incident light;
a second substrate portion (51, FIG. 19) stacked on a surface (top) of the first substrate portion (50+40+45+41) opposite to a surface (bottom) on which the light is incident and having a readout circuit (22+TR, FIG. 19) configured to output a pixel signal based on charge output from the pixel to a signal line; and
a through via (54, FIG. 19) configured to connect the first substrate portion (50+40+45+41) and the second substrate portion (51),
the pixel having a floating diffusion (FD, FIG. 19) configured to temporarily retain charge generated by photoelectric conversion,
the readout circuit (22+TR) having
a first pixel transistor (a transistor inside 22, FIG. 3) connected to the floating diffusion (FD) through the through via (54), and
a second pixel transistor (TR) connected to the first pixel transistor (a transistor inside 22) and the signal line, the through via (54) being provided, in plan view, between a contact portion provided at a gate electrode of the first pixel transistor (a transistor inside 22) and a contact portion provided at a gate electrode (TG, FIG. 19) of the second pixel transistor (TR) in a region of the pixel and in a position shifted in a second direction (left-right) orthogonal to a first direction (up-down) in which the contact portion of the first pixel transistor (a transistor inside 22) and the contact portion of the second pixel transistor (TR) are provided.
Regarding claim 2, Nakazawa discloses the light detection device according to claim 1, wherein the through via (54) is provided in a position shifted in the second direction (left-right) orthogonal to a wiring path configured to connect the contact portion of the first pixel transistor and the contact portion of the second pixel transistor (FIG. 19).
Regarding claim 3, Nakazawa discloses the light detection device according to claim 2, wherein current is passed from the first pixel transistor (a transistor inside 22) to the second pixel transistor (TR) in the wiring path (FIGs. 3 and 19).
Regarding claim 4, Nakazawa discloses the light detection device according to claim 1, further comprising a plurality of the pixels (FIG. 1) and a plurality of the readout circuits (FIG. 2), wherein at least some of the plurality of pixels form a shared pixel, the first pixel transistor and the second pixel transistor are shared between a plurality of pixels that form the shared pixel (FIG. 2).
Regarding claim 5, Nakazawa discloses the light detection device according to claim 4, wherein the through via is provided, in plan view, between the contact portion of the first pixel transistor provided in a first readout circuit and the contact portion of the second pixel transistor provided in a second readout circuit among the plurality of readout circuits and in a position shifted in the second direction orthogonal to the first direction in which the contact portion of the first pixel transistor and the contact portion of the second pixel transistor are provided (FIG. 1).
Regarding claim 6, Nakazawa discloses the light detection device according to claim 1, wherein in plan view, if the first direction corresponds to an x-coordinate and the second direction corresponds to a y- coordinate, the position coordinates of the contact portion of the first pixel transistor are (x1, y1), the position coordinates of the second pixel transistor are (x2, y2), and the position coordinates of the through-via are (x3, y3), x3 is a value between x1 and x2, and y3 is a value different from y1 and y2 (FIG. 19).
Regarding claim 7, Nakazawa discloses the light detection device according to claim 1, wherein in plan view, if the first direction corresponds to a y-coordinate, the second direction corresponds to an x- coordinate, the position coordinates of the contact portion of the first pixel transistor are (x1, y1), the position coordinates of the second pixel transistor are (x2, y2), and the position coordinates of the through-via are (x3, y3), x3 is a value different from xl and x2, and y3 is a value between y1 and y2 (x and y are relative direction, FIG. 19).
Regarding claim 8, Nakazawa discloses the light detection device according to claim 1, wherein the first pixel transistor is an amplification transistor (¶ [0126]) having a gate electrode connected to the floating diffusion (FD) to generate, as the pixel signal, a signal for voltage corresponding to a charge amount retained by the floating diffusion.
Regarding claim 9, Nakazawa discloses the light detection device according to claim 1, wherein the second pixel transistor (TR) is a selection transistor configured to control timing for outputting the pixel signal (FIG. 19).
Regarding claim 14, Nakazawa discloses an electronic device comprising a light detection device (see Nakazawa, FIG. 19), the light detection device comprising:
a first substrate portion (50+40+45+41, FIG. 19) having a pixel (41, ¶ [0127]) configured to photoelectrically convert incident light;
a second substrate portion (51, FIG. 19) stacked on a surface (top) of the first substrate portion (50+40+45+41) opposite to a surface (bottom) on which the light is incident and having a readout circuit (22+TR, FIG. 19) configured to output a pixel signal based on charge output from the pixel to a signal line; and
a through via (54, FIG. 19) configured to connect the first substrate portion (50+40+45+41) and the second substrate portion (51),
the pixel having a floating diffusion (FD, FIG. 19) configured to temporarily retain charge generated by photoelectric conversion,
the readout circuit (22+TR) having
a first pixel transistor (a transistor inside 22, FIG. 3) connected to the floating diffusion (FD) through the through via (54), and
a second pixel transistor (TR) connected to the first pixel transistor (a transistor inside 22) and the signal line, the through via (54) being provided, in plan view, between a contact portion provided at a gate electrode of the first pixel transistor (a transistor inside 22) and a contact portion provided at a gate electrode (TG, FIG. 19) of the second pixel transistor (TR) in a region of the pixel and in a position shifted in a second direction (left-right) orthogonal to a first direction (up-down) in which the contact portion of the first pixel transistor (a transistor inside 22) and the contact portion of the second pixel transistor (TR) are provided.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa et al. (US PG-Pub No.: 2021/0084249 A1, hereinafter, “Nakazawa”).
Regarding claim 10, Nakazawa discloses the light detection device according to claim 1.
Nakazawa is silent regarding that the first pixel transistor and the second pixel transistor have a planar shape.
However, it is well-known that a transistor can have a planar shape.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Nakazawa’s first pixel transistor and second pixel transistor having a planar shape, since it is an alternative design.
Regarding claim 11, Nakazawa discloses the light detection device according to claim 1.
Nakazawa is silent regarding that the first pixel transistor and the second pixel transistor have a fin shape having a three-channel structure.
However, it is well-known that a transistor can have a three-channel structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Nakazawa’s first pixel transistor and second pixel transistor having three-channel structure, since it is an alternative design.
Regarding claim 12, Nakazawa discloses the light detection device according to claim 1.
Nakazawa is silent regarding that the first pixel transistor and the second pixel transistor have an L shape with two channel directions.
However, it is well-known that a transistor can have an L shape with two channel directions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Nakazawa’s first pixel transistor and second pixel transistor having an L shape with two channel directions, since it is an alternative design.
Regarding claim 13, Nakazawa discloses the light detection device according to claim 1.
Nakazawa is silent regarding that the first pixel transistor and the second pixel transistor have a GAA (Gate All Around) shape having a four-channel structure.
However, it is well-known that a transistor can have a GAA shape having a four-channel structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Nakazawa’s first pixel transistor and second pixel transistor having a GAA shape having a four-channel structure, since it is an alternative design.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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/XIA L CROSS/Primary Examiner, Art Unit 2892
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