Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of the invention of Group I, claims 1-5, Embodiment A1 (Figs.2A-2C), Embodiment B1 (Fig.9), Embodiment C1 (Fig.16A), Embodiment D2 (Fig.18), Embodiment E7 (Figs.36-37), Embodiment F1 (Fig.60), and Embodiment G1 (Fig.69) in the reply filed on 7/17/2026 is acknowledged. The traversal is on the ground(s) that “examination of all of the identified inventions and all of the pending claims would not result in a serious search and/or examination burden.” This is not found persuasive because applicant asserts, in a conclusory manner, that examination of all identified inventions and pending claims would not result in a serious search and/or examination burden. However, applicant does not specifically address the reasons set forth in the restriction requirement. That is, the restriction requirement, dated 5/6/2026, identified groups I and II as lacking unity of invention (see restriction requirement, pg.3) and a species restriction of a disclosure that includes 72 figures (see restriction requirement, pgs.4-9) that would result in a serious search and/or examination burden, such as searching different inventive concepts, different claimed structures requiring different searches, etc. The aforementioned reasons were not addressed in the response.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to because there are no reference numbers and/or labels indicating the “parallel connection point” between the first series circuit and the second series circuit in claim 1, “first input terminal” in claims 4, 5, “one second input terminal” in claim 5, and “the other second input terminal” in claim 5. Note: Changes in the drawings may necessitate changes in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1, 3-5 objected to because of the following informalities:
Claim 1 recites “a first line… in which two or more switching elements are connected in series” further defined in claim 3 as “two or more diodes connected in series” and “a second line…in which three or more switching elements are connected in series” further defined in claim 3 as “…three or more diodes connected in series…” The examiner notes a “series” connection is a term known in the art and is defined as “connecting components or circuits so that they share the same current…” In applicant’s figs.36-37, however, there are multiple tapped intermediate nodes between the diodes 81-83, 91-93 where the current branches out. In other words, claim 1 and claim 3’s recitations of “connected in series” and applicant’s corresponding figures are inconsistent with what is understood in the art as a true series connection and, as such, the examiner believes there is no true “series” connection disclosed. The applicant is encouraged to amend the claims to positively recite the components and connections as illustrated in applicant’s figures. Appropriate connection is required.
Claim 4 recites the limitation “the first input terminal.” There is insufficient antecedent basis for this limitation in the claim. Additionally, claim 4 presents the first input terminal as completely arbitrary since it does not define what the first input terminal pertains to. The claim should further define what is intended by the first input terminal and connections of components corresponding to it. Appropriate correction is required.
Claim 5 recites “the other second input terminal”. There is insufficient antecedent basis for this limitation in the claim. Additionally, claim 5 should further define what is intended by the “other second input terminal” and connections of components corresponding to it.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by English Machine Translation of Kazuhiro et al. (JP 2008148414 A1).Regarding Claim 1,
Kazuhiro (fig.5) teaches a rectifier circuit, comprising:
a first line including a first series circuit (fig.5, pars [15, 37-38]; 30-1 has a first line including a first series circuit 31-11, 31-1n) in which two or more switching elements (fig.5, for e.g., two or more switching elements read on by diodes 64-1, 64-2 noting that a diode is a switching element as further defined in claim 2) are connected in series (see fig.5, pars [15, 38]; at least diodes 64-1, 64-2 are connected in series);
a second line including a second series circuit (fig.5, pars [15, 37-38]; 30-m has a second line including a second series circuit 31-m1, 31-mn) in which three or more switching elements are connected in series (fig.5, pars [15, 37-38]; for e.g., three or more switching elements read on by at least three unlabeled diodes of 30-m connected in series), the second series circuit being connected in parallel with the first series circuit (pars [9, 11, 15]; Kazuhiro teaches that the plurality of series circuits are connected in parallel between the output node N1 and the second output node N2. It is further noted that they are in parallel as the current path of the first series circuit is independent from that of the second series circuit);
one or more first antenna elements (fig.5, 12-11, pars [14, 40]) connected between the switching elements of the first series circuit (see fig.5, 12-11 connected to node between 64-1 and 64-2 in 30-1); and
one or more second antenna elements (fig.5, 12-m1, par [14]) connected between the switching elements of the second series circuit (see fig.5, 12m-1 connected to node(s) between diodes in 30-m),
wherein an output is extracted from a parallel connection point between the first series circuit and the second series circuit (see fig.5, pars [15, 39]; the output is extracted from a parallel connection point/output node N1 between the first and second series circuit).
Regarding Claim 2,
Kazuhiro teaches the claimed subject matter in claim 1 and further teaches each of the switching elements is a diode (fig.5, par [38]; the switching elements 64-1, 64-n are each a diode) or an FET.
Regarding Claim 3,
Kazuhiro teaches the claimed subject matter in claim 1 and further teaches wherein the first line includes a first diode series circuit in which two or more diodes are connected in series with a same polarity (fig.5, pars [15, 37-38]; first diode series circuit in 31-11 in which at least two or more diodes 64-1, 64-2 are connected in series with a same polarity- each diode points in the same direction with the cathode of 64-2 connected to the anode of 64-1), the second line includes a second diode series circuit in which three or more diodes are connected in series (fig.5, pars [15, 37-38]; second diode series circuit in 31-m1 in which at least three or more unlabeled diodes are connected in series) with the same polarity as that of the first diode series circuit (see fig.5, the second diode series circuit in 31-m1, similar to the first diode series circuit, has the cathode of 64-3 connected to the anode of 64-2 and the cathode of 64-2 connected to the anode of 64-1 and thus having the same polarity as that of the first diode series circuit), the second diode series circuit being connected in parallel with the first diode series circuit (pars [9, 11, 15]; Kazuhiro teaches that the plurality of diode series circuits are connected in parallel between the output node N1 and the second output node N2), one or more first antenna elements (fig.5, 12-11, par [14, 40]) are connected between the diodes of the first diode series circuit (see fig.5; first antenna element 12-11 connected via capacitor 63-1 between the diodes 64-1, 64-2 of the first diode series circuit), one or more second antenna elements (fig.5, 12-m1, par [14]) are connected between the diodes of the second diode series circuit (see fig.5; second antenna element 12-m1 connected via the capacitor between the unlabeled diodes of the second diode series circuit), and an output is extracted from a parallel connection point between the first diode series circuit and the second diode series circuit (see fig.5, par [15]; the output is extracted from a parallel connection point/output node N1 between the first and second series circuit).
Regarding Claim 4,
Kazuhiro teaches the claimed subject matter in claim 3 and further teaches wherein a DC-cut element (fig.5, par [38]; DC-cut element read on by capacitor 63-1 noting that this is the same structure disclosed for the DC-cut element by applicant’s fig.36) is connected between at least one diode connection point of the first diode series circuit and the first input terminal (see fig.5; 63-1 is connected between at least one diode connection point/node between 64-1 and 64-2 of the first diode series circuit and the first input terminal 61).
Regarding Claim 5,
Kazuhiro teaches the claimed subject matter in claim 3 and further teaches wherein the first diode series circuit includes a first diode (fig.5, diode 64-1) and a second diode (fig.5, diode 64-2), the first input terminal (61) is connected to a connection point between an anode of the first diode and a cathode of the second diode (see fig.5, Kazuhiro teaches the first input terminal 61 is connected to a connection point/node between an anode of first diode 64-1 and a cathode of second diode 64-2), the second diode series circuit includes a third diode (fig.5, topmost diode in 31-m1), a fourth diode (fig.5, second diode form the topmost diode in 31-m1), and a fifth diode (fig.5, the third diode from the topmost diode in 31-m1), and one second input terminal (fig.5, one second input terminal corresponding to the positive polarity side input terminal of 12-m1) is connected to a connection point between an anode of the third diode and a cathode of the fourth diode (see fig.5, the positive polarity input terminal of 12-m1 is connected to a connection point/node between an anode of the topmost diode/third diode and the cathode of the second diode from the topmost diode in 31-m1), and the other second input terminal (fig.5, negative polarity side input terminal of 12-m1) is connected to a connection point between an anode of the fourth diode and a cathode of the fifth diode (see fig.5; other second input terminal/negative side polarity input terminal of 12m-1 is connected to a connection point/node between an anode of the fourth diode/second from the topmost diode and cathode of the fifth diode/third diode from the topmost diode in 31-m1).
PRIOR ART DEEMED RELEVANT BUT NOT CURRENTLY RELIED UPON:
Daniel et al. (2016/0181867 A1)- Fig.8, par [44]; Daniel teaches a first line including a first series circuit (fig.8, par [44]; 130G-1 has a first line including a first series circuit of D1-D3) in which two or more switching elements are connected in series (see fig.8; diodes D1-D3 connected in series in that they have a dependent current path); a second line including a second series circuit (fig.8, par [44]; 130G-2 has a second line including a second series circuit of D1-D3) in which three or more switching elements are connected in series (fig.8, three or more switching elements read on by at least diodes D1-D3 connected in series in that they have a dependent current path in 130 G-2), the second series circuit being connected in parallel with the first series circuit (par [44]; Daniel teaches the harvesting devices are “connected in parallel between common ground sources and common system output nodes”-that is, the second series circuit is connected in parallel with the first series circuit via common ground connection and common Vout connection); one or more first antenna elements (fig.8, 120G-1, par [45]) connected between the switching elements of the first series circuit (see fig.8, 120G-1 connected to node between D1 and D2 in 130G-1); and one or more second antenna elements (fig.8, 120G-2, par [45]) connected between the switching elements of the second series circuit (see fig.8, 120G-2 connected to node between D1 and D2 in 130 G-2), wherein an output (fig.8, “Vout-sys”) is extracted from a parallel connection point (fig.8, see unlabeled parallel filled in node next to “Vout-sys”) between the first series circuit and the second series circuit (see fig.8).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RASEM MOURAD whose telephone number is (571)270-7770. The examiner can normally be reached M-F 9:00-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RASEM MOURAD/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
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